NDLI: A high-performance low-power highly manufacturable embedded DRAM technology using backend hi-k MIM capacitor at 40nm node and beyond

Content Provider	IEEE Xplore Digital Library
Author	Chen, C.Y. Chiang, W.C. Shen, C.Y. Tu, K.C. Tzeng, K.C. Lee, H.F. Huang, K.C. Cheng, Y.S. Chang, C.Y. Chu, H.C. Wang, C.J. Tsai, C.S. Oconnell, C.M. Hsieh, T.H. Chin, H.W. Wang, M.J. Wuu, S.G. Natarajan, S. Tran, L.C.
Copyright Year	2011
Description	Author affiliation: Taiwan Semiconductor Manufacturing Company, Ltd., 8, Li-Hsin Rd. 6, Hsin-Chu Science Park, Hsin-Chu, Taiwan 300-77, R.O.C. (Chen, C.Y.; Chiang, W.C.; Shen, C.Y.; Tu, K.C.; Tzeng, K.C.; Lee, H.F.; Huang, K.C.; Cheng, Y.S.; Chang, C.Y.; Chu, H.C.; Wang, C.J.; Tsai, C.S.; Oconnell, C.M.; Hsieh, T.H.; Chin, H.W.; Wang, M.J.; Wuu, S.G.; Natarajan, S.; Tran, L.C.)
Abstract	A highly manufacturable embedded DRAM technology at 40nm node is presented. This report provides the characterization data of 128Mbit embedded DRAM test vehicle fabricated by 40nm eDRAM 200MHz low power process. The test vehicle is composed of 32 macros and each macro unit is 4Mb with configuration 32k×128 bits. The process is cost effective and compatible to our low power Logic core process with three additional critical masks to the base process. The DRAM memory cell consists of a high performance pass gate transistor and a metal-insulator-metal (MIM) storage capacitor with a cell size of 0.0583 $um^{2}$ (< 1/4 of SRAM 0.242 $um^{2})$ and small macro size of 0.145 $mm^{2}$ per Mega bits (Mb). The stacked cell capacitor is formed using low temperature processed high-k dielectrics to achieve sufficient storage capacitance in DRAM cell. Low cell device leakage below 20 fA/cell at 105°C with silicided node process coupled with the high-k storage capacitance. The macro design for random access speed can operate from 25MHz to 200 MHz comparable to 6T SRAM. It has built-in ECC parity generation and correction circuits with memory storage space used for storing parity bits. The characterization is based on 200MHz, covering Vcc+/−15% at 125°C/ 105°C/ 25°C/ −40°C. Process corner skew includes core device corners TT/FS/SF/FF/SS and fast/slow cell device. Highly manufacturing yield of 128Mb macro is achieved to demonstrate the maturity of technology. The excellent cosmic ray (neutron) soft error rate (SER) performance of less than 4FITs/Mb is also achieved. The integration technologies can be applicable to the future embedded DRAM in 28nm, 20nm node and beyond.
Starting Page	1
Ending Page	2
File Size	216245
Page Count	2
File Format	PDF
ISBN	9781424484935
ISSN	19308868
e-ISBN	9781424484928
DOI	10.1109/VTSA.2011.5872231
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-25
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Performance evaluation Microprocessors Random access memory Capacitance Capacitors Transistors
Content Type	Text
Resource Type	Article

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