NDLI: Embedded dynamic random access memory

Content Provider	IEEE Xplore Digital Library
Author	Kirihata, T.
Copyright Year	2003
Description	Author affiliation: IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA (Kirihata, T.)
Abstract	For several decades, the 1-transistor Dynamic Random Access Memory (DRAM) has been the dominant choice for high density and low cost semiconductor memory in computing systems. Recently, advancements in miniaturization have allowed integration of DRAM on the same die with the processor. Key advancements in memory technology, architecture and circuit design required to capitalize on the merger of DRAM and logic are described here. After reviewing the history and accomplishments in embedded DRAM over the past decade, details of three generations of embedded DRAM development at IBM are discussed. In the third generation, which is the 130nm technology, three specialized DRAM macros have been developed. The first is a general purpose growable design targeted specifically for the ASIC's environment. The second is an area optimized design which includes special features for reducing standby and data retention current. The third macro employs a novel destructive read architecture with a single-ended direct sensing scheme for enabling random cycle time as fast as 3.3ns for network applications.
Starting Page	155
Ending Page	158
File Size	380549
Page Count	4
File Format	PDF
ISBN	0780377656
ISSN	1524766X
DOI	10.1109/VTSA.2003.1252576
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-06
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DRAM chips Random access memory Costs Semiconductor memory Computer architecture Memory architecture Circuit synthesis Corporate acquisitions Logic design Logic circuits
Content Type	Text
Resource Type	Article

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