NDLI: 22-nm damascene gate MOSFET fabrication with 0.9 nm EOT and local channel implantation

Content Provider	IEEE Xplore Digital Library
Author	Jeong-Dong Choe Chang-Sub Lee Sung-Ho Kim Sung-Min Kim Shin-Ae Lee Chang-Woo Oh Ju-Won Lee You-Gyun Shin Donggun Park Kinam Kim
Copyright Year	2003
Description	Author affiliation: R&D Center, Samsung Electron. Co., Kyungki-Do, South Korea (Jeong-Dong Choe)
Abstract	We have introduced a novel CMOS transistor fabrication technique using damascene gate with local channel implantation. This transistor has a benefit to reduce the resistance of source/drain extension without severe blanket channel implantation that causes large junction capacitance as well. Reliable process technologies were developed for the formation of channel length down to 22 nm. Gate patterns have no bumpy edges. Some new important processes for the fabrication of these small transistors are also introduced. Physical thickness of gate oxide was 0.9 nm with RTO. The 22 nm nMOSFETs are achieved with a drive current of 500 /spl mu/A//spl mu/m for an off current of 100 nA//spl mu/m at 1.0V. We obtained the hot carrier reliability exceeding 10 years for 1.0V operation.
Starting Page	68
Ending Page	71
File Size	232630
Page Count	4
File Format	PDF
ISBN	0780377656
ISSN	1524766X
DOI	10.1109/VTSA.2003.1252554
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-06
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Fabrication Capacitance Silicon compounds MOS devices Rapid thermal processing CMOS technology Space technology Dielectric substrates Computer aided engineering
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in