NDLI: Design and technology challenges for sub-0.5 mu m CMOS and bipolar

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1989 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers (Cat. No.89CH2631-0)

Design and technology challenges for sub-0.5 mu m CMOS and bipolar

Content Provider	IEEE Xplore Digital Library
Author	Ning, T.H.
Copyright Year	1989
Description	Author affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Ning, T.H.)
Abstract	The design and technology problems that must be solved in order to realize the potential performance of sub-0.5- mu m CMOS and bipolar devices are discussed. High-field and high-current-density effects are among the most important issues. The goal is to prevent these effects from becoming problems and yet achieve performance as expected from scaling. It is seen that there are no simple solutions. It is a matter of trading off performance with process complexity and/or reliability in an optimal manner. Scaling CMOS to about 50-nm channel length appears to be quite possible. However, scaling bipolar to much below 0.25 mu m requires more understanding of the device physics and major technology breakthroughs.
Starting Page	307
Ending Page	311
File Size	434539
Page Count	5
File Format	PDF
DOI	10.1109/VTSA.1989.68635
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-05-17
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Voltage Current density MOSFET circuits Power supplies Diodes MOS devices Inverters Power MOSFET Photonic band gap
Content Type	Text
Resource Type	Article

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