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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jhing Fa Wang Yuan Long Jeang Ming Hwa Sheu Jau Yien Lee |
| Copyright Year | 1989 |
| Description | Author affiliation: Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan (Jhing Fa Wang; Yuan Long Jeang; Ming Hwa Sheu; Jau Yien Lee) |
| Abstract | Two new register allocation concepts are presented. One is the concept of the profit of allocation, which minimizes the number of registers and the interconnection cost simultaneously. The other is the concept of cutting lifetime segment, which reduces the number of registers to a minimum. A global register allocation optimal algorithm (GRAOA), which obtains an optimal number of registers and near-optimal interconnection cost, is presented. This algorithm takes O(TR/sup 3/), where T is the number of slices and R is the minimum number of registers needed. |
| Starting Page | 126 |
| Ending Page | 128 |
| File Size | 301883 |
| Page Count | 3 |
| File Format | |
| DOI | 10.1109/VTSA.1989.68597 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1989-05-17 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Registers Cost function Design optimization Minimization methods Minimax techniques Partitioning algorithms Integer linear programming Algorithm design and analysis Design automation |
| Content Type | Text |
| Resource Type | Article |
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