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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pfiester, J.R. Lin, J.-H. Mocala, K. Ku, Y.-C. Higman, J. McNelly, T. Blackwell, M. Kaushik, V. James, B.M. Hegde, R.I. |
| Copyright Year | 1994 |
| Description | Author affiliation: Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA (Pfiester, J.R.; Lin, J.-H.; Mocala, K.; Ku, Y.-C.; Higman, J.; McNelly, T.; Blackwell, M.; Kaushik, V.; James, B.M.; Hegde, R.I.) |
| Abstract | Polysilicon thin-film transistors (TFT) are typically used in high-density SRAMs due to their low standby power dissipation and high on/off current ratio. However, as the bitcell area continues to decrease for higher density SRAMs circuit applications, less space is available for integrating the TFT into the bitcell. In this paper, a new TFT structure is proposed which is self-aligned to the underlying NMOS device, thereby providing a compact load element that exhibits excellent device performance at reduced power-supply voltages. The inverted-spacer TFT channel is formed in a narrow poly-filled lateral cavity around the inside perimeter of the bulk NMOS polysilicon gate stack. |
| Starting Page | 101 |
| Ending Page | 102 |
| File Size | 267144 |
| Page Count | 2 |
| File Format | |
| ISBN | 0780319214 |
| DOI | 10.1109/VLSIT.1994.324435 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1994-06-07 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Thin film transistors Random access memory MOS devices Annealing Dielectrics Oxidation Dry etching Resists Research and development Laboratories |
| Content Type | Text |
| Resource Type | Article |
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