NDLI: Data retention in ultra-thin-film-SOI DRAM with buried capacitor cell

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Data retention in ultra-thin-film-SOI DRAM with buried capacitor cell

Content Provider	IEEE Xplore Digital Library
Author	Nishihara, T. Moriya, H. Ikeda, N. Aozasa, H. Miyazawa, Y.
Copyright Year	1994
Description	Author affiliation: ULSI Res. & Dev. Lab., Sony Corp., Kanagawa, Japan (Nishihara, T.; Moriya, H.; Ikeda, N.; Aozasa, H.; Miyazawa, Y.)
Abstract	Data retention in DRAM cells with ultra-thin bonded SOI film is investigated using 256 kbit fully functional test chip of 0.4 /spl mu/m design rule. In order to minimize an accumulation of minority carriers in channel region, we adopt a PMOS cell transistor. As a result, a retention time of 47 seconds for 50% bit fail at 25/spl deg/C, which is determined by a subthreshold diffusion current in the cell transistor, is obtained. A possibility of further improvement in retention time is then discussed. An importance of an elimination of GIDL is also pointed out.
Starting Page	39
Ending Page	40
File Size	221347
Page Count	2
File Format	PDF
ISBN	0780319214
DOI	10.1109/VLSIT.1994.324388
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-06-07
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Capacitors Testing Bonding Bipolar transistors Temperature Laboratories Binary search trees Capacitance Surface topography
Content Type	Text
Resource Type	Article

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