NDLI: Cost and power/performance optimized 20nm SoC technology for advanced mobile devices

Content Provider	IEEE Xplore Digital Library
Author	Nallapati, G. Zhu, J. Wang, J. Sheu, J.Y. Cheng, K.L. Gan, C. Yang, D. Cai, M. Cheng, J. Ge, L. Chen, Y. Bucki, R. Bowers, B. Vang, F. Chen, X. Kwon, O. Yoon, S. Wu, C.C. Chidambaram, P. Cao, M. Fischer, J. Terzioglu, E. Mii, Y.J. Yeap, G.
Copyright Year	2014
Description	Author affiliation: Qualcomm Technol. Inc., San Diego, CA, USA (Nallapati, G.; Zhu, J.; Wang, J.; Gan, C.; Yang, D.; Cai, M.; Cheng, J.; Ge, L.; Chen, Y.; Bucki, R.; Bowers, B.; Vang, F.; Chen, X.; Kwon, O.; Yoon, S.; Chidambaram, P.; Fischer, J.; Terzioglu, E.; Yeap, G.) \|\| R&D, TSMC, Hsinchu, Taiwan (Sheu, J.Y.; Cheng, K.L.; Wu, C.C.; Cao, M.; Mii, Y.J.)
Abstract	A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.
Starting Page	1
Ending Page	2
File Size	356890
Page Count	2
File Format	PDF
ISBN	9781479933310
ISSN	21589682
e-ISBN	9781479933327
DOI	10.1109/VLSIT.2014.6894414
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Metals Logic gates Layout Optimization Mobile communication Computer architecture Performance evaluation
Content Type	Text
Resource Type	Article

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