NDLI: Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

Content Provider	IEEE Xplore Digital Library
Author	Kim, Y.S. Kodama, S. Mizushima, Y. Maeda, N. Kitada, H. Fujimoto, K. Nakamura, T. Suzuki, D. Kawai, A. Arai, K. Ohba, T.
Copyright Year	2014
Description	Author affiliation: DISCO Corp., Tokyo, Japan (Kawai, A.; Arai, K.) \|\| Fujitsu Labs. Ltd., Atsugi, Japan (Nakamura, T.) \|\| PEZY Comput. Ltd., Tokyo, Japan (Suzuki, D.) \|\| ICE Cube Center, Tokyo Inst. of Technol., Yokohama, Japan (Kim, Y.S.; Kodama, S.; Mizushima, Y.; Maeda, N.; Kitada, H.; Fujimoto, K.; Ohba, T.)
Abstract	An ultra-thinning down to 4-μm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-μm was approximately 1-μm within 300-mm wafer. No degradation in terms of retention characteristics and distribution employing 2Gb DRAM wafer was found after ultra-thinning. This suggests that no damage occurred due to thinning processes including wafer bonding and debonding steps. These results indicate good feasibility for multi-stack Wafer-on-Wafer (WOW) processes with the lowest aspect ratio of TSVs and parasitic capacitance, and enable multi-stacking for Tera-scale high density memory.
Starting Page	1
Ending Page	2
File Size	1021342
Page Count	2
File Format	PDF
ISBN	9781479933310
ISSN	21589682
e-ISBN	9781479933327
DOI	10.1109/VLSIT.2014.6894347
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Silicon Stress Degradation Through-silicon vias Positrons Surface treatment
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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