NDLI: Real-time MPEG-2 software decoding with a dual-issue RISC processor

Content Provider	IEEE Xplore Digital Library
Author	Holmann, E. Yamada, A. Yoshida, T. Uramoto, S.
Copyright Year	1996
Description	Author affiliation: Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan (Holmann, E.)
Abstract	A single chip system for real-time MPEG-2 decoding can be created by integrating a dual-issue RISC processor with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32 KB instruction RAM; and a 16 KB data RAM. The VLD hardware performs the Huffman decoding on the input data. The block loader performs the half-sample prediction for motion compensation and acts as a direct memory access controller for the RISC processor. The dual-issue RISC processor, running at 250 MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra blocks are decoded in less than 800 cycles, leading to a single chip, real-time MPEG-2 decoding system.
Starting Page	105
Ending Page	114
File Size	750680
Page Count	10
File Format	PDF
ISBN	0780331346
DOI	10.1109/VLSISP.1996.558309
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Reduced instruction set computing Hardware Real time systems Application software Digital signal processing Read-write memory Motion compensation Throughput Resource management
Content Type	Text
Resource Type	Article

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