NDLI: SHARP: efficient loop scheduling with data hazard reduction on multiple pipeline DSP systems

Content Provider	IEEE Xplore Digital Library
Author	Tongsima, S. Chantrapornchai, C. Sha, E. Passos, N.L.
Copyright Year	1996
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA (Tongsima, S.)
Abstract	Computation intensive DSP applications usually require a parallel/pipelined processor in order to achieve specific timing requirements. Data hazards are a major obstacle against the high performance of pipelined systems. This paper presents a novel efficient loop scheduling algorithm that reduces data hazards for those DSP applications. Such an algorithm has been embedded in a tool, called SHARP, which schedules a pipelined data flow graph to multiple pipelined units, while hiding the underlying data hazards and minimizing the execution time. This paper reports significant improvement for some well-known benchmarks, showing the efficiency of the scheduling algorithm and the flexibility of the simulation tool.
Starting Page	253
Ending Page	262
File Size	702165
Page Count	10
File Format	PDF
ISBN	0780331346
DOI	10.1109/VLSISP.1996.558358
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hazards Digital signal processing Pipeline processing Scheduling algorithm Hardware Computer applications Computer architecture Costs Processor scheduling Computer science
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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SHARP: efficient loop scheduling with data hazard reduction on multiple pipeline DSP systems