NDLI: A design space exploration framework for reduced bit-width Instruction Set architecture (rISA) design

Content Provider	IEEE Xplore Digital Library
Author	Halambi, A. Shrivastava, A. Biswas, P. Dutt, N. Nicolau, A.
Copyright Year	2002
Description	Author affiliation: Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA (Halambi, A.; Shrivastava, A.; Biswas, P.; Dutt, N.; Nicolau, A.)
Abstract	Code size is a critical concern in many embedded system applications, especially those using RISC cores. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, space-efficient (usually 16 bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature (termed rISA) can potentially reduce the code size by up to 50% with minimal performance degradation. However, contemporary processors incorporate only a simple rISA feature with severe restrictions on register accessibility. We present a compiler-in-the-loop Design Space Exploration framework that is capable of exploring various interesting rISA designs. We also present experimental results using this framework and show rISA designs that improve on the code size reduction obtained by existing rISA architectures.
Sponsorship	ACM SIGDA IEEE Comput. Soc
Starting Page	120
Ending Page	125
File Size	516236
Page Count	6
File Format	PDF
ISBN	1581135769
DOI	10.1145/581199.581228
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-02
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Space exploration Reduced instruction set computing Computer architecture Embedded system Computer aided instruction Embedded computing Registers Thumb Permission Read only memory
Content Type	Text
Resource Type	Article

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