NDLI: A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration

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2015 Symposium on VLSI Circuits (VLSI Circuits)

2014 Symposium on VLSI Circuits Digest of Technical Papers

Foreword: Welcome to the 2014 Symposium on VLSI Circuits

2014 VLSI circuits symposium committees

DataCenter 2020: Near-memory acceleration for data-oriented applications

Technology development for printed LSIs based on organic semiconductors

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution

A quad-channel 112–128 Gb/s coherent transmitter in 40 nm CMOS

A 40-Gb/s serial link transceiver in 28-nm CMOS technology

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering

Low power battery supervisory circuit with adaptive battery health monitor

A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83–92% efficiency across wide input and output voltages

A direct AC-DC and DC-DC cross-source energy harvesting circuit with analog iterating-based MPPT technique with 72.5% conversion efficiency and 94.6% tracking efficiency

A 13.56MHz wireless power transfer system with reconfigurable resonant regulating rectifier and wireless power control for implantable medical devices

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM

A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package

A peripheral switchable 3D stacked CMOS image sensor

An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range

A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier

7-bit 0.8–1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS

A 0.7V resistive sensor with temperature/voltage detection function in 16nm FinFET technologies

A monolithically-integrated chip-to-chip optical link in bulk CMOS

A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process

A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor

A power-harvesting pad-less mm-sized 24/60GHz passive radio with on-chip antennas

Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link

An ultra-low-power 2-step wake-up receiver for IEEE 802.15.4g wireless sensor networks

A 400MHz 10Mbps D-BPSK receiver with a reference-less dynamic phase-to-amplitude demodulation technique

A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with −76dBm sensitivity for high data rate wireless sensor networks

A 6.67mW sparse coding ASIC enabling on-chip learning and inference

A Vocabulary Forest-based object matching processor with 2.07M-vec/s throughput and 13.3nJ/vector energy in full-HD resolution

A 500MHz blind classification processor for cognitive radios in 40nm CMOS

A 13.1GOPS/mW 16-core processor for software-defined radios in 40nm CMOS

A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver

A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with −106dBc/Hz In-band noise using time amplifier based TDC

A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter

A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS

A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS

A 75dB DR 50MHz BW $3^{rd}$ order CT-ΔΣ modulator using VCO-based integrators

A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS

A 97.3 dB SNR, 600 kHz BW, 31mW multibit continuous time ΔΣ ADC

An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs

A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU

ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing

A low power and ultra high reliability LDPC error correction engine with Digital Signal Processing for embedded NAND Flash Controller in 40nm COMS

Application-aware solid-state drives (SSDs) with adaptive coding

An impedance and multi-wavelength near-infrared spectroscopy IC for non-invasive blood glucose estimation

A 6.5/11/17.5/30-GHz high throughput interferometer-based reactance sensors using injection-locked oscillators and ping-pong nested chopping

A 64×64 1200fps CMOS ion-image sensor with suppressed fixed-pattern-noise for accurate high-throughput DNA sequencing

A 4.7T/11.1T NMR compliant wirelessly programmable implant for bio-artificial pancreas in vivo monitoring

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline

Low V 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques

A 4.68Gb/s belief propagation polar decoder with bit-splitting register file

Early detection and repair of VRT and aging DRAM bits by margined in-field BIST

$2^{nd}$ generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology

A PVT-variation tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad

A 94GHz duobinary keying wireless transceiver in 65nm CMOS

A receiver architecture for intra-band carrier aggregation

A +22dBm IIP3 and 3.5dB NF wideband receiver with RF and baseband blocker filtering techniques

340mV–1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt $GF(2^{4})^{2}$ polynomials in 22nm tri-gate CMOS

R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS

A 7.11mJ/Gb/query data-driven machine learning processor $(D^{2}MLP)$ for big data analysis and applications

A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor

A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation

A millimeter-scale wireless imaging system with continuous motion detection and energy harvesting

A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range

An on-chip 72×60 angle-sensitive single photon image sensor array for lens-less time-resolved 3-D fluorescence lifetime imaging

320×240 oversampled digital single photon counting image sensor

A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit

A $4.78mm^{2}$ fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation

A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recording

An implantable continuous glucose monitoring microsystem in 0.18µm CMOS

A single-chip encrypted wireless 12-lead ECG smart shirt for continuous health monitoring

A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS

A 960MS/s DAC with 80dB SFDR in 20nm CMOS for multi-mode baseband wireless transmitter

A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOS

A 110mW, $0.04mm^{2},$ 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist

A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS

A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW

A 40-MHz 85.8%-peak-efficiency switching-converter-only dual-phase envelope modulator for 2-W 10-MHz LTE power amplifier

±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systems

An ASIC for readout of post-processed thin-film MEMS resonators by employing capacitive interfacing and active parasitic cancellation

15.4b incremental sigma-delta capacitance-to-digital converter with zoom-in 9b asynchronous SAR

A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation

A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging

A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology

An N-path filter enhanced low phase noise ring VCO

92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator

A 2.9mW, +/− 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration

A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS

A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration

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A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration

Content Provider	IEEE Xplore Digital Library
Author	Yuan Zhou Benwei Xu Yun Chiu
Copyright Year	2014
Description	Author affiliation: Univ. of Texas at Dallas, Dallas, TX, USA (Yuan Zhou; Benwei Xu; Yun Chiu)
Abstract	A 12b two-step pipelined SAR ADC reports a 66.7dB SNDR and an 86.9dB SFDR for a 5MHz sinusoidal input at 160MS/s. A digital background calibration based on opportunistic PN injection treats both DAC mismatch and residue-amplifier gain errors. The calibration enables a significant downsizing of the ADC input capacitance to yield a wideband, highly linear input network and an over-80dB SFDR while digitizing inputs from DC to 300MHz at full speed. The conversion FoM of this ADC is 20.7fJ/step at Nyquist. The prototype occupies an active area of $0.042mm^{2}$ in a 40nm CMOS low-leakage digital process.
Starting Page	1
Ending Page	2
File Size	681501
Page Count	2
File Format	PDF
ISBN	9781479933273
e-ISBN	9781479933280
DOI	10.1109/VLSIC.2014.6858454
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Calibration Capacitance Prototypes Detectors CMOS integrated circuits Time-domain analysis Clocks
Content Type	Text
Resource Type	Article

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