NDLI: An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration

Content Provider	IEEE Xplore Digital Library
Author	Seung-Chul Lee Elies, B. Yun Chiu
Copyright Year	2012
Description	Author affiliation: University of Illinois at Urbana-Champaign, USA (Seung-Chul Lee) \|\| University of Texas at Dallas, USA (Elies, B.; Yun Chiu)
Abstract	A 1-0 MASH ΔΣ ADC demonstrates a digital calibration technique treating both amplifier distortion and capacitor mismatch. The output-referred error analysis accurately models a nonlinear modulator. The identification of multiple error parameters is accomplished by correlating various moments of the ADC output with a one-bit pseudorandom noise (PN). The prototype ADC employing 29dB gain amplifiers measures 85dB SFDR and 67dB SNDR for a -1dBFS (1.1V) 5MHz sinusoidal input at 240MS/s. The core ADC consumes 37mW from a 1.25V supply and occupies $0.28mm^{2}$ in a 65nm CMOS low-leakage digital process, in which the transistor threshold voltages are around 0.5V.
Starting Page	164
Ending Page	165
File Size	299020
Page Count	2
File Format	PDF
ISBN	9781467308489
e-ISBN	9781467308496
e-ISBN	9781467308458
DOI	10.1109/VLSIC.2012.6243841
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Calibration Modulation Capacitors Multi-stage noise shaping Nonlinear distortion Prototypes Integrated circuit modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration