NDLI: A 10-bit 70 MS/s CMOS D/A converter

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2015 Symposium on VLSI Circuits (VLSI Circuits)

2014 Symposium on VLSI Circuits Digest of Technical Papers

2013 Symposium on VLSI Circuits

2012 Symposium on VLSI Circuits (VLSIC)

2011 Symposium on VLSI Circuits - Digest of Technical Papers

2010 Symposium on VLSI Circuits

2009 Symposium on VLSI Circuits

2008 IEEE Symposium on VLSI Circuits

2007 IEEE Symposium on VLSI Circuits

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

Symposium 1997 on VLSI Circuits

1996 Symposium on VLSI Circuits. Digest of Technical Papers

Digest of Technical Papers., Symposium on VLSI Circuits.

Proceedings of 1994 IEEE Symposium on VLSI Circuits

Symposium 1993 on VLSI Circuits

1992 Symposium on VLSI Circuits Digest of Technical Papers

1991 Symposium on VLSI Circuits

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

Embedded memory: a key to high performance system VLSIs

Future high performance ECL microprocessors

A high random-access-data-rate 4 Mb DRAM with pipeline operation

100 MHz serial access architecture for 4 Mb field memory

An experimental 2T cell RAM with 7 ns access time at low temperature

A divided/shared bitline sensing scheme for 64 Mb DRAM core

A 1.5 V circuit technology for 64 Mb DRAMs

Impacts of optoelectronics technology on ULSI

A 12.8-MHz sigma-delta modulator with 16-bit performance

The effect of dielectric relaxation on charge-redistribution A/D converters

A high-speed sample-and-hold technique using a Miller hold capacitance

A 13 bit 2.5 MHz self-calibrated pipelined A/D converter in 3 μm CMOS

A 10 b 10 MHz triple-stage Bi-CMOS A/D converter

A 6.8 ns 1 Mb ECL I/O BiCMOS configurable SRAM

A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy

An experimental 5 ns BiCMOS SRAM with a high-speed architecture

Fast-access BiCMOS SRAM architecture with a VSS generator

A 2 ns 16 K ECL RAM with reduced word line voltage swing

A 3.5 ns, 2 K×9 self timed SRAM

A 4-Mbit CMOS SRAM with 8-ns serial-access time

A 1 V operating 256-Kbit full CMOS SRAM

An 8 bit 150 MHz CMOS D/A converter with 2 Vp-p wide range output

A 10-bit 70 MS/s CMOS D/A converter

Ultra high sensitivity on-chip amplifier for VLSI CCD image sensor

A synthesis of 100 MHz monolithic third-order lowpass filters with a transmission zero

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

A 0.8 μm BiCMOS ATM switch on the 800 Mbps asynchronous buffered banyan network

A fully operational 1-kbit variable threshold Josephson RAM

A 7.6 K-gate Josephson macrocell array

A current sense-amplifier for fast CMOS SRAMs

A dynamic three-state memory cell for high-density associative processors

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

A new soft-error phenomenon in ULSI SRAMs-inverted dependence of soft-error rate on cycle time

A circuit design of intelligent CDRAM with automatic write back capability

Wordline coupling noise reduction techniques for scaled DRAMs

Environment and methodology for accurate noise simulation of VLSI circuits

PLL-based BiCMOS on-chip clock generator for very high speed microprocessor

Multi-emitter BiCMOS logic circuit family

Full-swing logic circuits in a complementary BiCMOS technology

Appraisal of BiCMOS from circuit voltage and delay time

NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit

A 36 ns 1 Mbit CMOS EPROM with new data sensing technique

High speed page mode sensing scheme for EPROMs and flash EEEPROMs using divided bit line architecture

A novel automatic erase technique using an internal voltage generator for 1 Mbit flash EEPROM

A 1 Mbit EEPROM with MONOS memory cell for semiconductor disk application

A 4 Mb 5 V-only flash EEPROM with sector erase

A 4-Mbit NAND-EEPROM with tight programmed $_{t}$ distribution

Pipelined, time-sharing access technique for a highly integrated multi-port memory

A proposed structure of a 4 Mbit content-addressable and sorting memory

Non-refreshing dynamic RAM for on-chip cache memories

An on-chip 72 K pseudo two-port cache memory subsystem

Architecture and design of a second-level cache chip with copy-back and 160 MB/s burst-transfer features

A current-mode column comparator circuit for high-speed, low-power on-chip cache-TAG memories

An experimental single-chip data flow CPU

Design of a 100 MHz hybrid number system data execution unit

A 140-MHz CMOS bit-level pipelined multiplier-accumulator using a new dynamic full-adder cell design

A 10 ns 54×54-bit parallel structured full array multiplier with 0.5 μm CMOS technology

1990 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. N.90CH2885-2)

VLSI circuit challenges for integrated sensing systems

Symposium 1989 on VLSI Circuits

Symposium 1988 on VLSI Circuits

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