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A 1.5-V, 10-bit, 200-MS/s CMOS Pipeline Analog-to- Digital Converter
| Content Provider | Semantic Scholar |
|---|---|
| Author | Devi, Manju Chavan, Arunkumar P. Muralidhara, K. N. |
| Copyright Year | 2014 |
| Abstract | Analog-to-digital converters (ADCs) are required in almost all communication and signal processing applications. This paper describes a 1.5-v, 10-bit, 200-Msample/s pipeline analog-todigital converter in 0.18-μm CMOS technology. The entire circuit architecture is built with a modular approach consisting of identical units organized into an easily expandable pipeline chain. The converter uses ten stage pipelined architecture with fully differential analog circuits, with a full-scale sinusoidal input at 10 MHz’s A special focus is made on pipelined ADC for its superior performance in terms of speed and resolution. General Terms Op-amp, Flip-flop, Adders, |
| Starting Page | 35 |
| Ending Page | 39 |
| Page Count | 5 |
| File Format | PDF HTM / HTML |
| DOI | 10.5120/15366-3869 |
| Volume Number | 88 |
| Alternate Webpage(s) | https://www.ijcaonline.org/archives/volume88/number7/15366-3869?format=pdf |
| Alternate Webpage(s) | https://doi.org/10.5120/15366-3869 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
