NDLI: Evaluation of modern gate oxide technologies to process charging

Content Provider	IEEE Xplore Digital Library
Author	Crook, D. Domnitei, M. Webb, M. Bonini, J.
Copyright Year	1993
Description	Author affiliation: Intel Corp., Hillsboro, OR, USA (Crook, D.; Domnitei, M.; Webb, M.; Bonini, J.)
Abstract	A CV/IV walk-out measurement technique that can be used to systematically determine the causes of various gate oxide yield and reliability problems is presented. By simultaneously measuring the effects trapped charge has on the (1) positive IV, (2) negative IV, and (3) CV as a function of charge injected through the oxide, it is possible to determine whether a particular oxide problem is a point defect or uniformly distributed, is a positive or negative trapping center, and has a centroid near the poly or substrate. This measurement technique can also be used to quantify the sensitivity a given gate oxide technology has to process charging. Three types of gate oxide technologies that are commonly used in VLSI manufacturing are evaluated using this technique. The results are compared with those taken by traditional techniques such as JT distributions and antenna structures.
Starting Page	255
Ending Page	261
File Size	641245
Page Count	7
File Format	PDF
ISBN	0780307828
DOI	10.1109/RELPHY.1993.283316
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-03-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Annealing Human computer interaction Measurement techniques Voltage Plasma applications Current measurement Charge measurement Particle measurements Manufacturing processes Thermal degradation
Content Type	Text
Resource Type	Article

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