NDLI: Novel self-stressing test structures for realistic high-frequency reliability characterization

Content Provider	IEEE Xplore Digital Library
Author	Snyder, E.S. Campbell, D.V. Swanson, S.E. Pierce, D.G.
Copyright Year	1993
Description	Author affiliation: Sandia Nat. Lab., Albuquerque, NM, USA (Snyder, E.S.; Campbell, D.V.; Swanson, S.E.; Pierce, D.G.)
Abstract	A series of self-stressing test structures suitable for investigation of reliability failure mechanisms (hot carriers, electromigration, oxide breakdown) under realistic integrated circuit operating conditions, is described. These structures contain DC-controlled, high-frequency on-chip oscillators, which stress test structures. As a result, high-frequency (>200-MHz) stress-testing can be performed using less expensive DC test systems. In particular, hot-carrier stress-testing was performed at frequencies up to 230 MHz, which is the highest stress frequency reported for inverters. For the 1- mu m technology examined, the quasi-static model accurately describes the degradation. The statistical variation in high-frequency, hot-carrier-induced degradation is presented, and variations with temperature are shown to be consistent with DC stress results. Since only DC test systems are needed, these structures provide a simple method to calibrate reliability simulators and characterize high-frequency reliability effects.
Starting Page	57
Ending Page	65
File Size	813183
Page Count	9
File Format	PDF
ISBN	0780307828
DOI	10.1109/RELPHY.1993.283301
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-03-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic testing Circuit testing Hot carriers Stress System testing Frequency Degradation Integrated circuit testing Integrated circuit reliability Failure analysis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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