NDLI: Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling

Content Provider	IEEE Xplore Digital Library
Author	Ecco, L. Ernst, R.
Copyright Year	2015
Description	Author affiliation: Inst. of Comput. & Network Eng., Tech. Univ. Braunschweig, Braunschweig, Germany (Ecco, L.; Ernst, R.)
Abstract	As DRAMs become faster, the penalty to reverse the direction of their data buses increases. Yet, existing real-time memory controllers do not reorder read and write commands. Hence, timing bounds are computed by assuming an alternating pattern of reads and writes, thus accounting for several data bus direction reversals, consequently leading to suboptimal results. Therefore, in this paper, we propose a memory controller that reorders read and write commands, which minimizes reversals. Moreover, we prove through a detailed timing analysis that the effect of the reordering is bounded. Finally, we compare our approach analytically with a state-of-the-art real-time memory controller and show that our timing bounds are up to 27% better.
Starting Page	53
Ending Page	64
File Size	384531
Page Count	12
File Format	PDF
ISBN	9781467395076
ISSN	10528725
DOI	10.1109/RTSS.2015.13
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real-time systems Delays DRAM chips Clocks Frequency measurement DRAM scheduling DRAM real-time read/write bundling DRAM command bundling read write overhead DRAM timing bounds DRAM analysis DRAM command overhead DRAM optimized schedling
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture Software

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