NDLI: Integrating the timing analysis of pipelining and instruction caching

Content Provider	IEEE Xplore Digital Library
Author	Healy, C.A. Whalley, D.B. Harmon, M.G.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci., Florida State Univ., Tallahassee, FL, USA (Healy, C.A.; Whalley, D.B.)
Abstract	Recently designed machines contain pipelines and caches. While both features provide significant performance advantages, they also pose problems for predicting execution time of code segments in real-time systems. Pipeline hazards may result in multicycle delays. Instruction or data memory references may not be found in cache and these misses typically require several cycles to resolve. Whether an instruction will stall due to a pipeline hazard or a cache miss depends on the dynamic sequence of previous instructions executed and memory references performed. Furthermore, these penalties are not independent since delays due to pipeline stalls and cache miss penalties may overlap. This paper describes an approach for bounding the worst-case performance of large code segments on machines that exploit both pipelining and instruction caching. First, a method is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. Next, these categorizations are used in the pipeline analysis of sequences of instructions representing paths within the program. A timing analyzer uses the pipeline path analysis to estimate the worst-case execution performance of each loop and function in the program. Finally, a graphical user interface is invoked that allows a user to request timing predictions on portions of the program.
Starting Page	288
Ending Page	297
File Size	1122491
Page Count	10
File Format	PDF
ISBN	0818673370
ISSN	10528725
DOI	10.1109/REAL.1995.495218
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-12-05
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Pipeline processing Delay Real time systems Hazards Performance analysis Computer science Graphical user interfaces Contracts Registers
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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