NDLI: Can the advantages of RISC be utilized in real time systems?

Content Provider	IEEE Xplore Digital Library
Author	Steininger, A. Schweinzer, H.
Copyright Year	1991
Description	Author affiliation: Insts. fur Elektrische Messtech., Tech. Univ. of Vienna, Austria (Steininger, A.; Schweinzer, H.)
Abstract	Within the last few years a lot of improvements have been made for processor architectures. Average and peak performance are increasing continuously. RISC, caching, pipelining and similar features have become indispensable to many systems. In critical real time systems, however, peak and average values are of minor interest. Because strict deadlines have to be met, only those values may be considered, that can be guaranteed even under adverse conditions. Features like reduced instruction set, caching, pipelining etc. are based upon statistical considerations and do not necessarily improve worst case performance. The question arises, whether new powerful processor architectures-especially the RISC architecture-are suitable for real time systems and if so, under which conditions. Some of the most important hardware features are analyzed to find an answer to this question.
Starting Page	30
Ending Page	35
File Size	398831
Page Count	6
File Format	PDF
ISBN	0818622105
DOI	10.1109/EMWRT.1991.144076
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-06-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing Real time systems Registers Pipeline processing Computer architecture Delay Hardware Modems Application software Contracts
Content Type	Text
Resource Type	Article

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