NDLI: Temperature-dependent scalable large signal CMOS device model developed for millimeter-wave power amplifier design

Content Provider	IEEE Xplore Digital Library
Author	Mallavarpu, N. Dawn, D. Laskar, J.
Copyright Year	2011
Description	Author affiliation: Georgia Electronic Design Center (GEDC), School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30308 USA (Mallavarpu, N.; Dawn, D.; Laskar, J.)
Abstract	As the gate length of CMOS processes has become smaller and the device fT has increased, applications such as CMOS power amplifiers in the millimeter-wave region have become feasible and practical. This paper describes the development of an empirical large-signal model for sub-100 nm CMOS transistors and demonstrates its successful use in the design of a 4-stage 60 GHz CMOS power amplifier with measured performance of 20dB gain, +10.3dBm P1dB, 13.5dBm Psat and 13% PAE. A novel drain-source current formulation is used, accurately modeling both strong-inversion and sub- threshold characteristics of short-channel, 90nm CMOS transistors. Further model enhancement is obtained through optimization for millimeter-wave applications using an optimized parasitic extraction process as well as the incorporation of size scalability and temperature dependency, making this modeling approach highly robust.
Starting Page	1
Ending Page	4
File Size	654004
Page Count	4
File Format	PDF
ISBN	9781424482931
ISSN	15292517
e-ISBN	9781424482924
e-ISBN	9781424482917
DOI	10.1109/RFIC.2011.5940692
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Integrated circuit modeling Power amplifiers Temperature measurement CMOS integrated circuits Solid modeling Millimeter wave transistors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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