NDLI: An integrated frequency synthesizer for 81–86GHz satellite communications in 65nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Zhiwei Xu Gu, Q.J. Yi-Cheng Wu Heng-Yu Jian Wang, F. Chang, M.-C.F.
Copyright Year	2010
Description	Author affiliation: University of California, Los Angeles, 90025, USA (Zhiwei Xu; Gu, Q.J.; Yi-Cheng Wu; Heng-Yu Jian; Wang, F.; Chang, M.-C.F.)
Abstract	We present an integrated frequency synthesizer in 65nm CMOS to enable the 81–86GHz satellite communication transceiver. The frequency synthesizer is inserted in a two-step zero-IF millimeter-wave transceiver with LO at 70–78GHz and LO at 1/8 of LO to cover the desired entire frequency bands. It also features coarse phase rotation to endow beam forming capabilities for the intended communication system. The phase noise is ≪ −83dBc/Hz at 1MHz offset as extrapolated from measured value at 1/8 of the VCO frequency (∼9.4GHz). The measured reference spur is ≪−49dBc. Total synthesizer power consumption including LO buffers and phase rotators is 65mW at 1V power supply and the compact layout has rendered small synthesizer core area of $0.16mm^{2}.$
Starting Page	57
Ending Page	60
File Size	350291
Page Count	4
File Format	PDF
ISBN	9781424462407
ISSN	15292517
e-ISBN	9781424462438
DOI	10.1109/RFIC.2010.5477388
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency synthesizers Satellite communication Transceivers Radio frequency Millimeter wave communication Phase noise Frequency measurement Noise measurement Phase measurement Voltage-controlled oscillators VCO Frequency Synthesizer injection locking divider multi-modulus programmable divider millimeterwave transceiver phase rotation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An integrated frequency synthesizer for 81-86ghz satellite communications in 65nm cmos.

A ${hbox{70}}{hbox{–}} {hbox{78-}}{hbox{GHz}}$ Integrated CMOS Frequency Synthesizer for $W$-Band Satellite Communications

Design of a 40GHz PLL frequency synthesizer with wide locking range ILFD in 65nm CMOS

Design of frequency synthesizer in frequency-hopping transceiver

A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

CMOS circuit techniques for millimeter-wave voltage-controlled oscillator and injection-locked frequency divider

A 4-GHz CMOS dual-modulus prescaler with enhanced input sensitivity over extended operation range

A 15 to 18-GHz Programmable Sub-Integer Frequency Synthesizer for a 60-GHz Transceiver

A 30 to 44 GHz divide-by-2, quadrature, direct injection locked frequency divider for sliding-IF 60 GHz transceivers

An integrated frequency synthesizer for 81–86GHz satellite communications in 65nm CMOS

Similar Documents

An integrated frequency synthesizer for 81-86ghz satellite communications in 65nm cmos.

A ${hbox{70}}{hbox{–}} {hbox{78-}}{hbox{GHz}}$ Integrated CMOS Frequency Synthesizer for $W$-Band Satellite Communications

Design of a 40GHz PLL frequency synthesizer with wide locking range ILFD in 65nm CMOS

Design of frequency synthesizer in frequency-hopping transceiver

A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

CMOS circuit techniques for millimeter-wave voltage-controlled oscillator and injection-locked frequency divider

A 4-GHz CMOS dual-modulus prescaler with enhanced input sensitivity over extended operation range

A 15 to 18-GHz Programmable Sub-Integer Frequency Synthesizer for a 60-GHz Transceiver

A 30 to 44 GHz divide-by-2, quadrature, direct injection locked frequency divider for sliding-IF 60 GHz transceivers

An integrated frequency synthesizer for 81–86GHz satellite communications in 65nm CMOS