NDLI: Vast-fast low-triggering LTdSCR ESD protection structure for RF ICs in CMOS

Content Provider	IEEE Xplore Digital Library
Author	Jian Liu Lin Lin Xin Wang Hui Zhao He Tang Qiang Fang Wang, A. Hongyi Chen Haolu Xie Siqiang Fan Bin Zhao Gary Zhang
Copyright Year	2010
Description	Author affiliation: Skyworks, China (Gary Zhang) \|\| Fudan University, China (Haolu Xie) \|\| Department of Electrical Engineering, University of California, Riverside, 92521, USA (Jian Liu; Lin Lin; Xin Wang; Hui Zhao; He Tang; Qiang Fang; Wang, A.) \|\| Tsinghua University, China (Hongyi Chen) \|\| Freescale Semi., China (Siqiang Fan; Bin Zhao)
Abstract	This paper reports design of a novel low-parasitic ultra-low-triggering voltage dual-directional LTdSCR ESD protection structure in foundry CMOS. It features programmable low triggering voltage of 4.7∼6V, low discharging resistance of ∼0.77Ω, low leakage of ∼0.1nA, extremely low parasitic capacitance of ∼10fF and ultra fast response of ∼100ps. it achieves ESD protection of ≫7.8kV HBM and ∼500V CDM for a 90µm device. Measurement matches simulation very well. This low-parasitic low-triggering ESD protection structure is suitable for high data rate and low-voltage RF ICs in CMOS.
Starting Page	233
Ending Page	236
File Size	496453
Page Count	4
File Format	PDF
ISBN	9781424462407
ISSN	15292517
e-ISBN	9781424462438
DOI	10.1109/RFIC.2010.5477278
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrostatic discharge Protection Radio frequency Thyristors Foundries Electric breakdown Low voltage Parasitic capacitance Radiofrequency integrated circuits Breakdown voltage SCR ESD low-parasitic RF IC CMOS
Content Type	Text
Resource Type	Article

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