NDLI: A 3GHz wideband ∑Δ fractional-N synthesizer with voltage-mode exponential CP-PFD

Content Provider	IEEE Xplore Digital Library
Author	Hedayati, H. Bakkaloglu, B.
Copyright Year	2009
Description	Author affiliation: Department of Electrical Engineering, Arizona State University, Tempe, 85287 USA (Hedayati, H.; Bakkaloglu, B.)
Abstract	A 3GHz wideband ∑Δ fractional-N synthesizer with an exponential settling voltage-mode PFD is presented. The 1MHz band-width Type-I PLL loop utilizes the exponential small-signal settling characteristics of a voltage-mode NMOS (follower) LDO based PFD-CP to reduce in-band quantization noise leakage by more than 13dB without the need for a noise suppression DAC. The PLL is fabricated on a 0.18μm CMOS process with less than 20-mA current consumption from 1.8-V power supply. The measured in-band phase noise at 100 kHz is −107dBc/Hz and out-of-band phase noise at 3 MHz is −130dBc/Hz. The PLL loop settling time for an accuracy of 0.1ppm and a frequency step of 45 MHz is less than 10μs.
Starting Page	325
Ending Page	328
File Size	416768
Page Count	4
File Format	PDF
ISBN	9781424433773
ISSN	15292517
DOI	10.1109/RFIC.2009.5135550
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wideband Synthesizers Voltage Phase locked loops Noise reduction Phase noise Phase frequency detector MOS devices Quantization CMOS process sigma-delta modulation fractional-N frequency synthesizers phase noise quantization noise
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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