NDLI: Single event gate rupture in 130-nm CMOS transistor arrays subjected to X-ray irradiation

Content Provider	IEEE Xplore Digital Library
Author	Silvestri, M. Gerardin, S. Faccio, F. Paccagnella, A.
Copyright Year	2009
Description	Author affiliation: Dipartimento di Ingegneria dell'Informazione, Università di Padova, via Gradenigo 6B, 35131 Padova, Italy (Silvestri, M.; Gerardin, S.; Paccagnella, A.) \|\| Physics Department, Microelectronics Group, CERN, 1211 Geneva 23, Switzerland (Faccio, F.)
Abstract	We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV $cm^{2}$ $mg^{−1}$ for devices previously irradiated up to 3 Mrad(SiO), and practically no change for 100 Mrad(SiO) irradiation, dose of interest for the future Super Large Hadron Collider (SLHC). We attribute this effect to the interplay between the damages produced by X rays, heavy ions, and electrical stress.
Starting Page	119
Ending Page	125
File Size	228442
Page Count	7
File Format	PDF
ISBN	9781457704925
ISSN	03796566
e-ISBN	9781457704932
DOI	10.1109/RADECS.2009.5994565
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-14
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Ions Leakage current Stress Radiation effects Transistors Electric breakdown SLHC ultra-thin gate oxides SEGR X-ray heavy ions gate rupture
Content Type	Text
Resource Type	Article

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