NDLI: Fast and slow border traps in MOS devices

Content Provider	IEEE Xplore Digital Library
Author	Fleetwood, D.M.
Copyright Year	1996
Description	Author affiliation: Sandia Nat. Labs., Albuquerque, NM, USA (Fleetwood, D.M.)
Abstract	Convergent lines of evidence are reviewed which show that near-interfacial oxide traps (border traps) that exchange charge with the Si can strongly affect the performance, radiation response, and long-term reliability of MOS devices. Observable effects of border traps include capacitance-voltage (C-V) hysteresis, enhanced 1/f noise, compensation of trapped holes, and increased thermally stimulated current in MOS capacitors. Effects of faster (switching times between /spl sim/10/sup -6/ s and /spl sim/1 s) and slower (switching times greater than /spl sim/1 s) border traps have been resolved via a dual-transistor technique. In conjunction with studies of MOS electrical response, electron paramagnetic resonance and spin dependent recombination studies suggest that E' defects (trivalent Si centers in SiO/sub 2/ associated with O vacancies) can function as border traps in MOS devices exposed to ionizing radiation or high-field stress. Hydrogen-related centers may also be border traps.
Starting Page	1
Ending Page	8
File Size	835381
Page Count	8
File Format	PDF
ISBN	0780330935
DOI	10.1109/RADECS.1995.509743
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-09-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOS devices Frequency Current measurement Time measurement Electron traps Charge measurement Electric variables measurement Capacitance-voltage characteristics Noise measurement Switches
Content Type	Text
Resource Type	Article

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