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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Roy, T. Meena, D. Prakasam, L.G.M. |
| Copyright Year | 2009 |
| Description | Author affiliation: LRDE, DRDO, CV Raman Nagar, Bangalore, India (Roy, T.; Meena, D.; Prakasam, L.G.M.) |
| Abstract | Array beam forming techniques exist that can yield multiple, simultaneously available beams. The beams can be made to have high gain and low sidelobe levels or controlled beam width. Beam forming techniques dynamically adjust the array pattern to optimize some characteristic of the received signal. Antenna arrays using beam-forming techniques can reject interfering signals having a direction of arrival different from that of desired signal. The principal reason of interest is their ability to automatically steer nulls into undesired sources of interferences, thereby reducing output noise and enhancing the detection of desired signal. Digital beam forming is thus a powerful technique for boosting the antenna performance. Our work emphasizes on the FPGA (Field Programmable Gate Array) based digital technique adopted for the implementation of fixed beam forming. This paper mainly focuses on the implementation solution provided by utilizing the efficient FPGA resources so as to meet the timings in the crucial application of beam forming. Extensive use of intellectual properties of Xilinx has been employed keeping in mind the time efficiency it provides. Beam forming and beam scanning are generally accomplished by phasing the feed to each element of an array so that signals received from all the elements will be in phase in particular direction. This is the direction of the maximum beam.The FPGA based approach facilitates the design with high degree of flexibility, reliability and upgradeability. The implementation also overcomes the main difficulty of compensating minute propagation delays often encountered while using beam forming for radar applications. The paper discusses all the critical implementation issues that are taken care of in the development of the efficient FPGA structure for implementation. |
| Starting Page | 1 |
| Ending Page | 5 |
| File Size | 522639 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424428700 |
| ISSN | 10975659 |
| DOI | 10.1109/RADAR.2009.4977109 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-05-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Phased arrays Radar antennas Automatic control Directive antennas Antenna arrays Interference Noise reduction Signal detection Boosting |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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