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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cai Chenxi Wang Xiutan Peng Yingning |
| Copyright Year | 2001 |
| Description | Author affiliation: Dept. of Electron. Eng., Tsinghua Univ., Beijing, China (Cai Chenxi) |
| Abstract | The design of modern electronic systems demands high system reliability and maintainability. In order to perform fault detection, localization and isolation effectively, it is necessary to design a built-in self-testing (BIST) module specific to the corresponding system. This paper presents a BIST method based. on compressed 2-dimensional signature analysis. The principle of compression and performance of test are discussed in detail. Using the presented method, a high faulty coverage ratio (FCR) can be achieved with a short signature compressed in both time domain and space domain. Theoretical analysis shows that this method is reliable and it can be easily implemented in hardware. |
| Sponsorship | Chinese Inst. Electron. (CIE) |
| Starting Page | 885 |
| Ending Page | 888 |
| File Size | 323919 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780370007 |
| DOI | 10.1109/ICR.2001.984853 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-10-15 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Built-in self-test Circuit testing Circuit faults Maintenance Fault detection Power system reliability Hardware Shift registers Performance analysis Time domain analysis |
| Content Type | Text |
| Resource Type | Article |
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