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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xu Junyi Wang Xiutan Peng Yingning |
| Copyright Year | 2001 |
| Description | Author affiliation: Dept. of Electron. Eng., Tsinghua Univ., Beijing, China (Xu Junyi) |
| Abstract | In order to fulfil real time signal processing tasks such as clutter rejection, moving target detection (MTD) and constant false alarm rate (CFAR) control in airborne radar, an airborne radar parallel signal processing system (ARPS2) is proposed with DSP chips as its kernel processing nodes. The DSP chips are used with parallel architecture. Each node has its private input and output memory. It adopts several parallel techniques, such as parallel storage, parallel processing, parallel code loading and parallel data organization to achieve high efficiency. It has a simple structure, excellent flexibility and easiness in developing. ARPS2 is going to be applied to an airborne radar. It can also be applied to perform high-speed real time signal processing algorithms in other kinds of radar. |
| Sponsorship | Chinese Inst. Electron. (CIE) |
| Starting Page | 792 |
| Ending Page | 795 |
| File Size | 368659 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780370007 |
| DOI | 10.1109/ICR.2001.984832 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-10-15 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Airborne radar Radar signal processing Digital signal processing chips Real time systems Clutter Object detection Control systems Kernel Parallel architectures Parallel processing |
| Content Type | Text |
| Resource Type | Article |
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