NDLI: Low-latency distance protective relay on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Yifan Wang Dinavahi, V.
Copyright Year	2014
Description	Author affiliation: Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada (Yifan Wang; Dinavahi, V.)
Abstract	The need for high-speed multi-function protective relays in both traditional transmission systems and the new emerging paradigm of the smart grid is growing. As a widely used protective scheme for transmission lines, a distance relay's high speed and reliable operation to clear faults is essential. This paper proposes a real-time low-latency hardware digital distance protective relay on the field programmable gate array (FPGA). Taking advantage of inherent hard-wired architecture of the FPGA, the proposed hardware distance relay design is paralleled and fully pipelined to achieve low latencies in various relay modules which are developed in textual VHDL language. This low-latency feature allows fast operating and data throughput so that the relay can handle high-frequency sampled data and reach higher computational efficiency. In addition, the parallelism and hardwired architecture of the FPGA makes the design more reliable in computation than the sequential software-based numeric relay. The FPGA-based distance relay can operate on both phasor-based signals and instantaneous signals with 2.09 microseconds and 0.35 microseconds latency respectively based on the clock frequency of 100 MHz. The hardware relay is tested in real-time by feeding it with generated faulted current and voltage data for typical faults and the relay response recorded. The results demonstrate the speed and effectiveness of the hardware distance relay.
Starting Page	1
Ending Page	1
File Size	66969
Page Count	1
File Format	PDF
ISBN	9781479964154
DOI	10.1109/PESGM.2014.6938859
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-07-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protective relaying Field programmable gate arrays Hardware Reliability Real-time systems Computer architecture
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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