NDLI: FPLD implementation of a PN-matched filter correlator

Content Provider	IEEE Xplore Digital Library
Author	Harvey, B.A. Bouey, C.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Florida State Univ., Tallahassee, FL, USA (Harvey, B.A.; Bouey, C.)
Abstract	Typical spread-spectrum receivers use a sliding correlator to achieve synchronization with a received direct sequence spread spectrum (DSSS) signal. A faster approach (lower latency) to synchronization that uses much shorter synchronization preambles is to use a parallel or tapped delay line correlator to implement a pseudorandom noise (PN) matched filter. Surface acoustic wave (SAW) devices, charge coupled devices (CCD) and digital signal processing (DSP) components are commonly used to implement PN-matched filters. An analysis of a tapped delay line implementation of a PN-matched filter using field programmable logic devices (FPLD) is presented. A pipelined architecture is used to accelerate the calculations and improve the speed of the matched filter. The analysis and simulations show that using standard FPLDs a 16-chip PN-matched filter with a 4-bit, soft-decision input can be implemented with a sampling rate in excess of 100 MHz. If 2X over sampling is used in the absence of chip synchronization, this translates to a chip rate over 50 Mcps and a data rate in excess of 3 Mbps. Therefore, this filter is feasible and even advantageous for moderate speed wireless networks, particularly those with small packet lengths or requiring low latency.
Sponsorship	IEEE Region 3 IEEE Jamaican Section Univ. of Technol, Jamaica Univ. of the West Indies
Starting Page	44
Ending Page	50
File Size	414459
Page Count	7
File Format	PDF
ISBN	0780378563
DOI	10.1109/SECON.2003.1268429
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-04-04
Publisher Place	Jamaica
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Correlators Spread spectrum communication Delay lines Matched filters Digital signal processing Sampling methods Acoustic noise Surface acoustic wave devices Acoustic waves Surface acoustic waves
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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