NDLI: Characterizing state devices for switching noise

Content Provider	IEEE Xplore Digital Library
Author	Hodson, R.F. Bampton, A.E.H. Knipp, P.A.
Copyright Year	1997
Description	Author affiliation: Dept. of Phys. & Comput. Sci., Christopher Newport Univ., Newport News, VA, USA (Hodson, R.F.)
Abstract	Greater processing power has given rise to modern EDA tools which allow detailed analog analysis of ASIC power distribution networks. Switching noise can now be accurately simulated and monitored throughout the I/O rings and core electronics. These EDA tools can generate warning messages when simulated switching noise values exceed user-specified maximum acceptable levels. Unfortunately, maximum allowable switching noise is not accurately approximated based on V/sub IL/ levels, V/sub IH/ levels, and gate switching speed. This study determines the sensitivity of state devices (flip-flops and latches) to switching noise using a simulation-based approach and the 0.8 micron CMOSX standard cell library. Sensitivities to noise on clock and asynchronous inputs are characterized in terms of switching voltage and pulse duration. Maximum allowable noise levels are presented for many CMOSX state devices. Also, two conclusions were reached: (1) acceptable levels of switching noise may vary greatly between state devices and (2) minor design changes may greatly improve susceptibility to switching noise.
Starting Page	276
Ending Page	277
File Size	503142
Page Count	2
File Format	PDF
ISBN	0780338448
DOI	10.1109/SECON.1997.598690
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-04-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise level Electronic design automation and methodology Application specific integrated circuits Power systems Monitoring Noise generators Flip-flops Latches Libraries Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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