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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Vaziri, S. Smith, A.D. Henkel, C. Ostling, M. Lemme, M.C. Lupina, G. Lippert, G. Dabrowski, J. Mehr, W. |
| Copyright Year | 2012 |
| Description | Author affiliation: Leibniz-Institut für Innovative Mikroelektronik, IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany (Lupina, G.; Lippert, G.; Dabrowski, J.; Mehr, W.) || School of Information and Communication Technology KTH Royal Institute of Technology 16440 Kista, Sweden (Vaziri, S.; Smith, A.D.; Henkel, C.; Ostling, M.; Lemme, M.C.) |
| Abstract | In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for microelectronics integration: bottom gates with ultra-thin (2nm) high-quality thermally grown SiO dielectrics, shallow trench isolation between devices and atomic layer deposited Al top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing and other graphene-based devices. |
| Starting Page | 250 |
| Ending Page | 253 |
| File Size | 2094861 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467317078 |
| ISSN | 19308876 |
| e-ISBN | 9781467317085 |
| e-ISBN | 9781467317061 |
| DOI | 10.1109/ESSDERC.2012.6343380 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-09-17 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Aluminum oxide Dielectrics Silicon Transistors Films |
| Content Type | Text |
| Resource Type | Article |
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