NDLI: A 32-channel modular bi-directional neural interface system with embedded DSP for closed-loop operation

Content Provider	IEEE Xplore Digital Library
Author	Peng Cong Karande, P. Landes, J. Corey, R. Stanslaski, S. Santa, W. Jensen, R. Pape, F. Moran, D. Denison, T.
Copyright Year	2014
Description	Author affiliation: Dept. of Biomed. Eng., Washington Univ., St. Louis, MO, USA (Karande, P.; Landes, J.; Moran, D.) \|\| Medtronic Neuromodulation, Minneapolis, MN, USA (Peng Cong; Corey, R.; Stanslaski, S.; Santa, W.; Jensen, R.; Pape, F.; Denison, T.)
Abstract	A prototype bi-directional neural interface system is presented with closed-loop and embedded DSP capabilities. The system includes 32-electrode stimulation capability, eight multiplexed low-noise low-power bio-potential sensing channels with on-chip digital FFT, and a Cortex M3-based microcontroller for implementing closed-loop algorithms. The stimulation subsystem can provide a maximum stimulation current of 12mA with approximately 3% accuracy per channel. The sensing subsystem uses a fully differential chopping amplifier achieving a noise floor <;100nV/rtHz with approximately 1μA current from 2V supply. A 13bit continuous-time sigma-delta ADC is used to sample the amplifier output at the rate of 33kHz. The ADC consumes approximately 100nA while achieving an ENOB of 12b with a 250Hz date rate. A hardware implementation of a cached-FFT is included in the sensing IC to perform spectral analysis of the bio-potential signal. The resulting multiple spectral signatures can be selectively sent to the microcontroller allowing for algorithmic control of the stimulator system. The system partition was designed to minimize overall computational power while providing user flexibility. The sensing performance of the prototype has been demonstrated with 2-D cursor control in a non-human primate brain machine interface (BMI) model using 20 features simultaneously.
Starting Page	99
Ending Page	102
File Size	3940327
Page Count	4
File Format	PDF
ISBN	9781479956944
ISSN	19308833
e-ISBN	9781479956968
DOI	10.1109/ESSCIRC.2014.6942031
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-22
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sensors Noise Electrodes Prototypes Algorithm design and analysis Microprocessors embedded DSP neural interface CMOS circuit implantable system low noise low power amplifier
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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