NDLI: A CMOS 120 mW 8-bit Voltage Output Video DAC using a Current-Cell Matrix

Content Provider	IEEE Xplore Digital Library
Author	Fournier, J.M. Abrial, A. Lelah, A. Senn, P. Bouvier, J.
Copyright Year	1987
Description	Author affiliation: CNS, chemin du vieux chene, BP.98 38240 MEYLAN FRANCE (Fournier, J.M.; Abrial, A.; Lelah, A.; Senn, P.; Bouvier, J.)
Abstract	This paper describes an 8-bit CMOS video speed D/A converter fabricated in a 2.4 ¿m CMOS technology. In order to achieve monotonicity and static linearity, a current cell-matrix configuration has been used. The linearity errors due to the voltage drop along the reference lines has been reduced by the choice of a small full-scale current (2 mA). A very simple cell structure has been adopted to reduce the matrix area. In order to perform a high speed operation, a high speed decoding circuit with one stage latches has been developed. The design of a transimpedance amplifier at the output of the matrix allows a fast settling time with a low impedance output. The experimental results show that the maximum convertion rate is 33 Mhz, the dc integral and differential linearity errors are 0.25 LSB and the typical power consumption is 120 mW. Recent developments in digital TV, and high picture quality requirements will lead to a more general use of an efficient and low cost video digital to analog converter. New video decoder architectures [1] and the introduction of the MAC standard [2] for direct satellite broadcasting have created a need for triple 8-bit D/A converters in the range of 27 Mhz for the sampling rate. Efficient architectures using CMOS technology have been proposed [3,4] which guarantee monotonicity and small area requirements.
Starting Page	105
Ending Page	107
File Size	471263
Page Count	3
File Format	PDF
ISBN	3800715341
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1987-09-23
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Berlin: VDE-Verlag, 1987
Subject Keyword	Voltage CMOS technology Linearity Matrix converters Decoding Circuits Latches Impedance Energy consumption Digital TV
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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