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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | van Dijk, S. Hely, D. |
| Copyright Year | 2001 |
| Description | Author affiliation: Philips Research Laboratories Eindhoven, The Netherlands (van Dijk, S.) |
| Abstract | Usually it is thought that cross-talk is deleterious for signal integrity. However, by propagating the same signal over aggressor and victim wires, the victim wire delay is minimised because its lateral capacitance to the aggressors is virtually reduced at the spatial position of the travelling waves. We exploit this cross-talk property to build a 3-wire scheme for interconnect delay reduction, which we also refer to as the booster approach. This approach was experimentally verified on a test-chip, fabricated in a 0.18µm CMOS technology. We observed a 5x-delay reduction over the nominal wire delay. Based on simulations, we further provide a comparison of this novel approach to other well-known approaches like repeater insertion and the fat-wire approach. |
| Starting Page | 301 |
| Ending Page | 304 |
| File Size | 222814 |
| Page Count | 4 |
| File Format | |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-09-18 |
| Publisher Place | Austria |
| Access Restriction | Subscribed |
| Rights Holder | Non IEEE |
| Subject Keyword | Delay Decision support systems Fiber reinforced plastics |
| Content Type | Text |
| Resource Type | Article |
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