NDLI: A 900MHz/1.9GHz integrated transceiver and synthesizer IC for GSM

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ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)

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Table of contents

Future is in wireless!

Ultra-low voltage CMOS cascode amplifier

Curvature compensated BiCMOS bandgap with 1 V supply voltage

Front-end processor core for up to 64X speed CD-ROM drive in 0.35um CMOS

A dynamically controllable DC/DC level converter and its application to high-speed, low-power circuits

Bluetooth: From antenna to silicon

A micropower class AB CMOS log-domain filter for DECT applications

Low-voltage analog filters using floating-gate MOSFETs

A 400MHz 5th-order CMOS continuous-time switched-current ΣΔ modulator

A 1.8V MOSFET-only sigma-delta modulator using compensated MOS-capacitors in depletion with substrate biasing

A 73dB SFDR 10.7MHz 3.3V CMOS bandpass ΣΔ modulator sampled at 37.05MHz

A low-power 1GHz super-regenerative transceiver with time-shared PLL control

A CMOS 2V quadrature direct up-converter chip for DCS-1800 integration

A 900MHz/1.9GHz integrated transceiver and synthesizer IC for GSM

A 2-GHz low-power single-chip CMOS receiver for WCDMA applications

A low stress 20dBm power amplifier for LINC transmission with 50% peak PAE in 0.25 µm CMOS

A 700MHz, 1W fully differential class E power amplifier in CMOS

A universal dual band LNA implementation in SiGe-technology for wireless applications

A 9mW, 900-MHz CMOS LNA with 1.05dB-noise-figure

Using capacitive cross-coupling technique in RF low noise amplifiers and down-conversion mixer design

A low power reconfigurable 12-tap FIR interpolation filter with fixed coefficient sets

Optimum voltage swing on on-chip and off-chip interconnects

$Itanium^{TM}processor$ system bus design

Self calibrating and adjustable CMOS pad driver for improved electromagnetic compatibility

A new contactless smartcard IC using an on-chip antenna and an asynchronous micro-controller

Fully integrated motor driver controller for hard disk drive using digital approach

High-speed and low-swing on-chip bus interface using threshold voltage swing driver and dual sense amplifier receiver

Iterative self-timed multiplier with early completion

Low power self-timed floating-point divider in 0.25um technology

"Software-radio base-stations, a challenge for analog IC-design"

Battery supplied low power analog-digital front-end for audio applications

A 147 dB dynamic range electronic attenuator for audiometric applications with on-chip 1 W power amplifier

Analog design in deep sub-micron CMOS

An eighth-order CMOS lowpass filter with 30-120 Mhz tuning range and programmable boost

Programmable direct digital tuning circuit for a continuous-time filter

SOI CMOS circuit design exposed — Another dirty tricks campaign?

A 350 MHz programmable analog FIR filter using mixed-signal multiplier

A 2.7V CMOS dual-mode baseband filter for PDC and WCDMA

A high IP3 RF receiver chip set for mobile radio base stations up to 2 GHz

High performance SiGe upconverter for double conversion tuner

1.0-volt, 9-bit pipelined CMOS ADC

A low-power 14-b 5 MS/s CMOS pipeline ADC with background analog self-calibration

12 bit low power fully differential switched capacitor non-calibrating successive approximation ADC with 1MS/s

An 8-bit 13-Msamples/s digital-background-calibrated algorithmic ADC

A dual-phase-controlled dynamic latched (DDL) amplifier for high-speed and low-power DRAMs

A high-efficiency back-bias generator with cross-coupled hybrid pumping circuit for sub-1.5 V DRAM applications

A low power reconfigurable I/O DRAM macro with single bit line writing scheme

A 1-V, 3.44-ns, 4.1-mW at 50-MHz, 128-Kb four-way set-associative CMOS cache memory implemented by 1.8V 0.18µm foundry CMOS technology for low-voltage low-power VLSI system applications

A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM wireless receivers

Measurements and analysis of PLL jitter caused by digital switching noise

Split-drain MOST based circuit for measuring electric power

Low power column ADC for CMOS imagers

Ultra low power A/D converters using an enhanced differential charge-transfer amplifier

SiGe track-and-hold with HD=-87 dBFS for f=110 MHz, f=(110 MHz-1 kHz) and V=1 V

A 2.5 volt 6 bit 600MS/s flash ADC in 0.25µm CMOS

An 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter

A 2.7 50MHz IF-sampling DS-modulator with +37dBV IIPfor digital cellular phones

Adaptive noise shaping ADC based on LMS algorithm

A digitally programmable burst-mode 155 Mb/s transmitter for PON

A 0.8 µm SOI CMOS on-board data handling bus modem for satellite applications

A 12 GHz/128 frequency divider in 0.25µm CMOS

An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with < 10-Hz RF carrier resolution

A 500MHz supply noise insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter

A novel structure for DCO PLLs with equivalent 16 bit digital phase quantization, digital loop filter and 18ps long-term jitter

A channel selection filter for a WCDMA direct conversion receiver

CMOS switched-capacitor decimation filter for mixed-signal video applications

A CMOS g-C polyphase filter with high image band rejection

A CMOS switched-capacitor bandpass filter with 100 Msample/s input sampling and frequency downconversion

A Hilbert sampler/filter and complex bandpass SC filter for I/Q demodulation

A low-distortion digitally programmable continuous-time filter and variable-gain amplifier

An analog CMOS high-speed continuous-time FIR filter

APD implementation to GHz range receiver channel for a pulsed time-of-flight laser radar

A low-power microphone preamplifier with EMI canceling

A 2.8V 200MHz replicating current comparator for convolutional decoders

New regulated voltage down converter based on modified band-gap cells

A 2GHz low-distortion low-noise two-stage LNA employing low-impedance bias terminations and optimum inter-stage match for linearity

A high dynamic range 3.4 GHz CMOS micropower mixer

Generating all 2-transistor circuits leads to new wide-band CMOS LNAs

A self-calibrating 900-MHz CMOS image-reject receiver

A new small signal modeling of RF MOSFETs including charge conservation capacitances

Influence of substrate noise on RF performance

A 2.7 V, 8 GHz monolithic I/Q RC oscillator with active inductive loads

5 GHz low-noise bipolar and CMOS monolithic VCO's

A fully integrated sub-1 V 4 GHz CMOS VCO, and a 10.5 GHz oscillator

Dynamically programmable parallel processor (DPPP): A novel reconfigurable architecture with simple program interface

Transition pattern coding: An approach to reduce energy in interconnect

Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design

Investigation of cell leakage and data retention in eDRAM

Source-pulsed dynamic-threshold CMOS SRAMs for fast, portable applications

A low-power SRAM with resonantly powered data, address, word, and bit lines

Super-compact shared-cache memories with low power consumption for multi-issue single chip processors

Nonvolatile CMOS latch employing GMR resistors

Dynamic flip-flop with improved power

Future trends in automotive electronics, sensors and communication systems

A programmable intraocular CMOS pressure sensor system implant

A low-power ASK demodulator for inductively coupled implantable electronics

VDSL, from concept to chips

SC interface and calibration circuit for a CMOS humidity sensor

A position detection sensor for 3-D measurement

3-D ICs: Motivation, performance analysis, and technology

A skew-tolerant design scheme for over 1-GHz LSIs

A novel high speed low power logic family: Race logic

Skewed CMOS: Noise-immune high-performance low-power static circuit family

A receiver channel with a leading edge timing discriminator for a pulsed time-of-flight laser radar

A packaged low-noise high-speed regulated cascode transimpedance amplifier using a 0.6µm N-well CMOS technology

A 1.8V 20mW $1mm^{2}14b$ 100Msample/s CMOS DAC

A 10-bit 200 MS/s CMOS parallel pipeline A/D converter

A differentially tuned 1.73GHz-1.99GHz quadrature CMOS VCO for DECT, DCS1800 and GSM900 with a phasenoise over tuning range between -128dBc/Hz and -137dBc/Hz at 600 kHz offset

A comparison of MOS varactors in fully-integrated CMOS LC VCO's at 5 and 7 GHz

A low-voltage low-power 0.25µm CMOS ADSL analog front-end IC

A mixed-signal CMOS MODEM ASIC for data transmission on the low-voltage power-line with sensitivity of 283µVrms at 10Kbps

LVDS I/O cells with rail-to-rail receiver input for SONET/SDH at 1.25Gb/s

A 10 Gb/s, 120/60 mA laser/modulator driver IC with dual-mode actively matched output buffer

New fast-lock PLL for mobile GSM GPRS applications

A 2 GHz ΔΣ fractional-N frequency synthesizer in 0.35 µm CMOS

An analogue delay line for virtual clock enhancement in DDS

Conference timetable

"Best paper award '99"

Proceedings of the 25th European Solid-State Circuits Conference

Proceedings of the 24th European Solid-State Circuits Conference

Proceedings of the 23rd European Solid-State Circuits Conference

ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference

ESSCIRC '95: Twenty-first European Solid-State Circuits Conference

ESSCIRC '94: Twientieth European Solid-State Circuits Conference

ESSCIRC '93: Nineteenth European Solid-State Circuits Conference

ESSCIRC '92: Eighteenth European Solid-State Circuits conference

ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference

ESSCIRC '90: Sixteenth European Solid-State Circuits Conference

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

ESSCIRC '88: Fourteenth European Solid-State Circuits Conference

ESSCIRC '87: 13th European Solid-State Circuits Conference

ESSCIRC '86: Twelfth European Solid-State Circuits Conference

ESSCIRC '85: 11th European Solid-State Circuits Conference

ESSCIRC '84: Tenth European Solid-State Circuits Conference

ESSCIRC '83: Ninth European Solid-State Circuits Conference

ESSCIRC '82: Eighth European Solid-State Circuits Conference

ESSCIRC '81: 7th European Solid State Circuits Conference

ESSCIRC 80: 6th European Solid State Circuits Conference

Fifth European Solid State Circuits Conference - ESSCIRC 79

ESSCIRC 78: 4th European Solid State Circuits Conference - Digest of Technical Papers

ESSCIRC '77: 3rd European Solid State Circuits Conference

ESSCIRC 76: 2nd European Solid State Circuits Conference

1975 First European Solid State Circuits Conference (ESSCIRC)

A 900MHz/1.9GHz integrated transceiver and synthesizer IC for GSM

Content Provider	IEEE Xplore Digital Library
Author	Magoon, R. Joo Leong Tham Molnar, A. Pregardier, B. Margarit, M. Conta, M. Cheng, J. Ali, A. Lloyd, S.
Copyright Year	2000
Description	Author affiliation: Conexant Systems, Newport Beach, CA (Magoon, R.)
Abstract	An integrated GSM compliant 2.7V, 900MHz/1.9GHz dual band transceiver with an I and Q interface including a dual integer N synthesizer is presented. The receiver provides a total of 110dB of gain range with 80dB of programmable gain range at IF selectable in steps of 2dB and 30dB of programmable gain range in the baseband selectable in steps of 10dB. An on-chip track and hold based DC offset correction scheme is provided to remove DC offsets before each receive slot in a GSM application. An on chip VHF oscillator achieves a phase noise level of -106dBc/Hz at 100kHz offset when operating at 800MHz and the synthesizer provides a close-in phase noise performance of better than -78dBc/Hz at 1kHz offset. The frequency translation loop based transmit section achieves an unwanted sideband suppression of -40dBc, LO leakage of -42dBc, and third order spurious rejection of -69dBc. The transmit output noise level is -165dBc/Hz at a 20MHz offset from the carrier.
Starting Page	53
Ending Page	56
File Size	318678
Page Count	4
File Format	PDF
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-19
Access Restriction	Subscribed
Rights Holder	Non IEEE
Subject Keyword	Transceivers Synthesizers Integrated circuit synthesis GSM Phase noise Dual band Baseband Oscillators Frequency locked loops Noise level
Content Type	Text
Resource Type	Article

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