NDLI: A 0.5µm CMOS $10^{6}transistors$ analog programmable array processor for real–time image processing

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Table of contents

Digital Processing – future aspects of the semiconductor business

VLSI memory technology: Current status and future trends

Highly integrated RF–ICs for GSM, DECT and UMTS systems a status review and development trends

Comparing and combining photonics and electronics in information transmission and processing

High speed electronics interfacing fiber networks

Automotive semiconductor technologies for the new millennium

CMOS or CCD image sensors for digital still applications?

Sensor systems – interface between environment and application

A 40µw, 75dB dynamic range, 70kHz bandwidth biquad filter based on complementary MOS transconductors

A 100MHz partial analog adaptive equalizer for use in wired data transmission

A 60–350 MHz programmable analog filter in a digital CMOS process

An eight–order lowpass filter with 5–100 Mhz tuning range and programmable boost

A chopper modulated instrumentation amplifier with first order low–pass filter and delayed modulation scheme

Integrated lock–in amplifier for sensor applications

A 500MHz write amplifier for hard disk drives with low output impedance

A high speed low noise CMOS MR preamplifier for disk drives

Low–power BiCMOS Op Amp with integrated current mode charge pump

A 200MHz IF, 11 bit, 4th order band–pass ΔΣ ADC in SiGe

A 3.3V CMOS 10.7MHz 6th–order bandpass ΣΔ modulator with 78dB dynamic range

14–bit, 2.2MS/s sigma delta ADCs

A 13.5–bit cost optimized multi–bit delta–sigma ADC for ADSL

A low power ASIC for the control of a mobile micro–actuator array

Single chip, self supplied, voltage and charge mode double 80V piezoelectric actuator driver

Electronic processing for 10Gbit/s dispersion supported transmission systems

A 1.3 GOPS parallel DSP for high performance image processing applications

2.44 GFLOPS 300MHz floating–point vector processing unit for high performance 3D graphics computing

Investigation on low voltage, low power silicon bipolar design topology for high speed digital circuits

A low–voltage energy scalable static differential logic $(ES^{2}DL)$ family

Dual threshold voltage domino logic

Split gates: A low swing technique for reducing power for high fanout gates

Area–efficient multiport memories for the Tb/s bandwidth era

A 32Mb–4b/cell analog flash memory supporting variable density with 3V–only supply and serial I/O

A low–jitter mixed DLL for high–speed DRAMs

High speed capacitive coupled interface for multipoint connections

A 5.3GHz programmable divider for HiPerLAN in 0.25µm CMOS

An improved low power crystal oscillator

A monolithic 0.4 mW SOA LC voltage–controlled oscillator

Reducing MOSFET 1/f noise and power consumption by "Switched biasing"

A 500MS/sec–54dB THD S/H circuit in a 0.5µm CMOS process

A 0.5µm CMOS analog RAM chip for real–time video processing

An analog baseband circuitry for a WCDMA direct conversion receiver

A 15–bit pipelined floating–point A/D converter

An 8–bit low–voltage pipelined ADC utilizing switched–opamp technique

A 1mW delta–sigma ADC with fully integrated baseband module for GSM application

A 1.8–3.3V high speed current steering DAC embedded core

Modeling of digital substrate noise generation and experimental verification using a novel substrate noise sensor

Circuit technique for accurate soft error rate measurements

Low supply voltage fully integrated CMOS VCO with three terminals spiral inductor

Fully–integrated low phase noise bipolar differential VCOs at 2.9 and 4.4 GHz

Impact of indirect stability on phase noise performance of fully–integrated LC tuned VCOs

A fully integrated 2 GHz LC–VCO with phase noise of –125 dBc/Hz at 600kHz

A 2.7V, 2.64GHz fully integrated synchronous oscillator for WLAN applications

A wideband linearisation technique for non–linear oscillators using a multi–stage polyphase filter

Microelectronic components for a retina implant system

A fully integrated sensor interface chip

A multichannel CMOS interface IC for recording car–crash conditions

ASK 10% demodulator for contactless smart card IC

Asynchronous 250 Mbit/s optical receivers with integrated detector in standard CMOS technology for optocoupler applications

164 Ms/s tape drive channel IC with 4 independent digital peak detect read/write channels and automatic tape speed tracking over a 3:1 range

Vertically integrated sensors for advanced imaging applications

A high dynamic range CMOS image sensor for automotive applications

A low noise accelerometer with digital PID–type controller and multibit force feedback

An absolute air pressure smart sensor family with 2 dimensional calibration

A 256×256–pixel smart CMOS image sensor for line based stereo vision applications

Design of an integrated photo detector circuit for laser doppler blood flow monitoring

An 85 MHz IF bandpass sigma–delta modulator for CDMA receivers

A 170MHz quadrature down–converter in 0.8µm BiCMOS for very low power pagers

A 200 MHz sub–mA RF front end for wireless hearing aid applications

RF circuits technique of dual–band transceiver IC for GSM and DCS1800 applications

A 200MHz IF BiCMOS chip for linear LINC transmitters

First integrated bipolar RF PA family for cordless telephones

A high–speed CMOS on–chip temperature sensor

Integrated optoelectronic receiver for a pulsed time–of–flight laser radar

A 66 × 66 pixels analog edge detection array with digital readout

A low–cost high–accuracy CMOS smart temperature sensor

An adaptive bio–inspired analog silicon retina

An 8–bit and a 10–bit low power high–speed neuron MOS digital–to–analog converter in 0.04 $mm^{2}$

A CMOS 10bit 37MS/s pipelined A/D converter with code regeneration and averaging

Design for optimum performance–to–power ratio of a continuous–time ΣΔ modulator

A ΣΔ modulator with extended supply voltages in 0.8µm SOI CMOS for direct ground referred instrumentation interfacing

A CMOS 12–bit 15 Msample/s digitally self–calibrated pipelined A/D converter

An 1.1–GHz packaged CMOS VCO with phase noise of – 126 dBc/Hz at a 600–kHz offset

A two–bit ΔΣ–modulator with 83dB SNDR for digital cellular telephones

Algorithmic design of a 900MHz CMOS RF power amplifier using SPICE–Smith chart method

Second order distortion in CMOS direct conversion receivers for GSM

A 1.8GHz BiCMOS RF receiver IC taking into account the cross modulation for CDMA wireless applications

A bandpass sigma–delta demodulator for digital radio

New high performance and wide range tunable two–stage 3GHz CMOS RF hetero–linked oscillators

A 0.5µm CMOS $10^{6}transistors$ analog programmable array processor for real–time image processing

All–analog decoder for a binary (18,9,5) tail–biting trellis code

A high resolution time–to–digital converter for ultrasonic flow measurement

A 1V active RC filter with on–chip frequency and Q tuning

A 100MHz CMOS g–C bandpass filter

A 1.5 V, 30 Msps, 9– to 10–bit equivalent current–mode CMOS sample–and–hold circuit

A low–voltage CMOS transconductor for very high frequencies

Programmable voltage multipliers for pacemaker output pulse generation in CMOS 0.8 µm technology

A 430MHz, –52dB THD, single transconductor, 3rd–order low–pass filter and its extension to a 5th–order, in a 0.5µm CMOS process

Robust digitization and digital non–uniformity correction in a single–chip CMOS camera

Advanced CMOS and BiCMOS photonic receiver ICs

A CMOS nonsecond–to–millivolt converter

A low–power truly–modular 1.8GHz programmable divider in standard CMOS technology

Design and optimization of sense–amplifier–based flip–flops

A low–power quadtree fractal image decoder

A bootstrapped latched CMOS logic family with demand–on boosting for low–power application

ECL-CMOS logic LSI technology using 20 GHz latch with CMOS test circuits

A 250MHz low voltage swing bus driver for embedded memory logic

ASPRO: An asynchronous 16-bit RISC microprocessor with DSP capabilities

Distributed active clock network

Production DC screening techniques for RF performances of bipolar ICs

A 5-parameter mismatch model for short channel MOS transistors

Proceedings of the 24th European Solid-State Circuits Conference

Proceedings of the 23rd European Solid-State Circuits Conference

ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference

ESSCIRC '95: Twenty-first European Solid-State Circuits Conference

ESSCIRC '94: Twientieth European Solid-State Circuits Conference

ESSCIRC '93: Nineteenth European Solid-State Circuits Conference

ESSCIRC '92: Eighteenth European Solid-State Circuits conference

ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference

ESSCIRC '90: Sixteenth European Solid-State Circuits Conference

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

ESSCIRC '88: Fourteenth European Solid-State Circuits Conference

ESSCIRC '87: 13th European Solid-State Circuits Conference

ESSCIRC '86: Twelfth European Solid-State Circuits Conference

ESSCIRC '85: 11th European Solid-State Circuits Conference

ESSCIRC '84: Tenth European Solid-State Circuits Conference

ESSCIRC '83: Ninth European Solid-State Circuits Conference

ESSCIRC '82: Eighth European Solid-State Circuits Conference

ESSCIRC '81: 7th European Solid State Circuits Conference

ESSCIRC 80: 6th European Solid State Circuits Conference

Fifth European Solid State Circuits Conference - ESSCIRC 79

ESSCIRC 78: 4th European Solid State Circuits Conference - Digest of Technical Papers

ESSCIRC '77: 3rd European Solid State Circuits Conference

ESSCIRC 76: 2nd European Solid State Circuits Conference

1975 First European Solid State Circuits Conference (ESSCIRC)

A 0.5µm CMOS $10^{6}transistors$ analog programmable array processor for real–time image processing

Content Provider	IEEE Xplore Digital Library
Author	Linan, G. Foldesy, P. Espejo, S. Dominguez-Castro, R. Rodriguez-Vazquez, A.
Copyright Year	1999
Description	Author affiliation: Instituto de Microelectrónica de Sevilla, Sevilla, Spain (Linan, G.)
Abstract	A 64×64 Analog Programmable Array Processor chip in 0.5µm CMOS technology is presented. The new prototype has been designed to process and provide either analog (8bits greyscale) or binary (black and white) images. Analog and digital I/O rates are 1MHz and 10MHz respectively. Accuracy in the generation of voltage weight signals is slightly below 8bits (7.6 bits). The chip has been demonstrated to be able to perform satisfactory a large variety of image processing tasks. Experimental results of two brand new features, namely analog edge extraction and movement detection in greyscale images, are provided in this paper.
Starting Page	358
Ending Page	361
File Size	78307
Page Count	4
File Format	PDF
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-09-21
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Editions Frontieres
Subject Keyword	CMOS process Image processing Cellular neural networks Prototypes CMOS technology Circuits Signal processing Process design Image edge detection Application software
Content Type	Text
Resource Type	Article

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