NDLI: Analog VLSI implementation of early vision edge detection with noise suppression and image segmentation

Content Provider	IEEE Xplore Digital Library
Author	Yi, C.-H. Schlabbach, R. Kroth, H. Karner, A. Hohn, J. Klar, H.
Copyright Year	1998
Description	Author affiliation: Technical University of Berlin, Berlin, Germany (Yi, C.-H.)
Abstract	We present an analog VLSI implementation of a new multiplexed two-layer parallel resistive network for early vision edge detection with noise suppression and image segmentation. One layer of the network is multiplexed to implement both Gaussian filtering and image segmentation by using the extracted edge information to control its horizontal resistors. The vertical resistors are realized by linearized operational transconductance amplifiers (OTA) with dual outputs to feed both network layers from a single input. The horizontal resistors are realized with single MOS transistors. Their gates are supplied with voltages higher than the supply voltage V., which are generated on-chip by a charge pumping circuit to ensure operation in the linear region while using small transistor dimensions. For edge detection, a new method for zero-crossing determination was implemented using an analog multiplier and a current comparator. To suppress incorrectly detected edges caused by noise, a special chopper circuit was applied.
Starting Page	304
Ending Page	307
File Size	464276
Page Count	4
File Format	PDF
DOI	10.1109/ESSCIR.1998.186269
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-09-22
Publisher Place	The Netherlands
Access Restriction	Subscribed
Rights Holder	Editions Frontieres
Subject Keyword	Very large scale integration Image edge detection Image segmentation Resistors Voltage Circuits Information filtering Information filters Data mining Transconductance
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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