NDLI: A 0.8 nVspl radic/Hz CMOS preamplifier for magneto-resistive read elements

Content Provider	IEEE Xplore Digital Library
Author	Robinson, M.E. Klein, H.W. Palla, S. Chung, T.-S.
Copyright Year	1994
Description	Author affiliation: Hacienda Design Lab., IMP, Pleasanton, CA, USA (Robinson, M.E.; Klein, H.W.; Palla, S.; Chung, T.-S.)
Abstract	State-of-the-art tape drives now employ MR heads to achieve increased bit density and speed-independent signal amplitude. In such systems, the preamplifier (PA) has to support simultaneous reading of up to four signals from up to eight magneto-resistive (MR) read elements. Hence, thermal considerations require a minimum power consumption architecture. Due to manufacturing and wear out, head impedances from 20 to 150 /spl Omega/ must be allowed. The need for optimizing the read elements operating point also requires the integration of four programmable low-noise current sources. To allow for backward compatibility, the PA should amplify very large input signals at low distortion levels. Previous PA designs make use of expensive BiCMOS technology, have no on-chip low-noise current DACs, and do all the signal processing in the voltage-mode. This paper describes how CMOS technology can be used to achieve sub-nVspl radic/Hz noise levels counting contributions from both the amplifier and the bias-current sources. It also describes how large dynamic range and high PSRR are achieved by combining current and voltage-mode signal processing. The actual chip designed contains four preamps, four bias DACs for the read elements, an 8:4 input multiplexer, and a serial interface. It is realized in 1.2 /spl mu/m CMOS technology.
Starting Page	252
Ending Page	253
File Size	353043
Page Count	2
File Format	PDF
ISBN	0780318447
DOI	10.1109/ISSCC.1994.344652
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-02-16
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Preamplifiers CMOS technology Magnetic heads Signal processing Voltage Energy consumption Manufacturing Impedance Distortion Signal design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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