NDLI: A system-integrate ULSI chip containing eleven 4 Mb RAMs, six 64 kb SRAMs and an 18 k gate array

Content Provider	IEEE Xplore Digital Library
Author	Sato, K. Fujita, K. Miyazawa, H. Shirai, M. Kobayashi, M. Ishihara, M. Nakao, T.
Copyright Year	1992
Description	Author affiliation: Hitachi Ltd., Tokyo, Japan (Sato, K.; Fujita, K.; Miyazawa, H.; Shirai, M.; Kobayashi, M.; Ishihara, M.; Nakao, T.)
Abstract	The authors describe the realization of a ULSI chip that makes system integration possible on a silicon die, not in wafer-scale integration. They consider chip configuration, packaging, defect relief, fabrication, and evaluation results. This system-integrated ULSI chip (SYSI-ULSI) contains eleven standard 4-Mb DRAMs, six standard 64-kb SRAMs, 200 I/O pins, and an 18-k gate array. The DRAMs are laid out on both sides of the chip. The 200 I/O pins are located on the upper and lower sides of the chip, and the gate array is laid out at the center to reduce the length of the channel between it and each part and eliminate skew between channels by equalizing their lengths. The 38.1650.4 mm/sup 2/ SYSI-ULSI chip is packaged in a 324-pin 5486 mm/sup 2/ plastic grid array package. A Cu/W thermal spreader is used for die-bonding. A cavity-down package is used for low thermal resistance with a heat sink. Power dissipation is 3.9 W.
Starting Page	52
Ending Page	53
File Size	228148
Page Count	2
File Format	PDF
ISBN	0780305736
DOI	10.1109/ISSCC.1992.200406
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-02-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ultra large scale integration Pins Plastic packaging Thermal resistance Silicon Wafer scale integration Fabrication Resistance heating Heat sinks Power dissipation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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