NDLI: A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array

Content Provider	IEEE Xplore Digital Library
Author	Sato, K. Kobayashi, M. Hida, H. Miyazawa, H. Shirai, Y. Fujita, K. Nakao, T. Ishihara, M.
Copyright Year	1966
Abstract	A system integrated LSI chip (SLSI) that contains eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array, for a graphics application system is described. To implement the SLSI on a silicon chip, three key techniques have been developed: (1) system redundancy for defect relief; (2) chip configuration and fabrication with blade masking to achieve a hybrid 38.1650.4-mm/sup 2/ chip; and (3) large-capability and high-reliability 324-pin 5486-mm/sup 2/ plastic pin grid array package. Using a system redundancy technique, a 60% yield for the SLSI is achieved with a 40% yield for the DRAM itself. That is twice the 30% yield of the conventional repair scheme. Access times are 65 ns for the DRAM and 14 ns for the SRAM with a 3.9-W chip power dissipation.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1608
Ending Page	1613
Page Count	6
File Size	718732
File Format	PDF
ISSN	00189200
Volume Number	27
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Large scale integration Packaging Logic arrays Graphics Redundancy Fabrication Nonvolatile memory Control systems Cache memory
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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