NDLI: A 3.9 /spl mu/m pixel pitch VGA format 10 b digital image sensor with 1.5-transistor/pixel

Please wait, while we are loading the content...

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

2012 IEEE International Solid-State Circuits Conference

2011 IEEE International Solid-State Circuits Conference

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

2004 IEEE International Solid-state Circuits Conference Digest of Technical Papers

Embedded-systems for a connected world

Table of contents

SE1 Architectures and Circuits for Ultra Wideband Radio

SE2 CMOS-Based Bio Sensors

SE3 Highlights of DAC

Session 1 Overview: Plenry Session

Processors and memory: the drivers of embedded systems toward the networked world

Emerging technology and business solutions for system chips

Cellular phones as embedded systems

Session 2 Overview: Non-Volatile Memory

A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

An experimental 256 Mb non-volatile DRAM with cell plate boosted programming technique

A 4Mb 0.18 /spl mu/m 1T1MTJ Toggle MRAM memory

Embedded flash memory for security applications in a 0.13 /spl mu/m CMOS logic process

A 55 mm/sup 2/ 256 Mb NROM flash memory with embedded microcontroller using an NROM-based program file ROM

A 0.9 V 1T1C SBT-based embedded non-volatile FeRAM with a reference voltage scheme and multi-layer shielded bit-line structure

A 3.3 V 4 Gb four-level NAND flash memory with 90 nm CMOS technology

Session 3 Overview: Processors

Design and implementation of the POWER5/spl trade/ microprocessor

A dual-core 64 b UltraSPARC microprocessor for dense server applications

A 40 Gb/s network processor with PISC/spl trade/ dataflow architecture

A scalable X86 CPU design for 90 nm process

Dynamic voltage and frequency management for a low-power embedded microprocessor

A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor

PowerPC 970 in 130 nm and 90 nm technologies

Session 4 Overview: Oversampled ADCs

A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 67dB dynamic range in 10MHz bandwidth

A 25 MS/s 14 b 200 mW /spl Sigma//spl Delta/ modulator in 0.18 /spl mu/m CMOS

/spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC

A 0.9 V 1.5 mW continuous-time /spl Delta//spl Sigma/ modulator for WCDMA

A 1 V 88 dB 20 kHz /spl Sigma//spl Delta/ modulator in 90 nm CMOS

A power optimized 14-bit SC /spl Delta//spl Sigma/ modulator for ADSL CO applications

A mirror image free two-path bandpass /spl Sigma//spl Delta/ modulator with 72 dB SNR and 86 dB SFDR

A 2 mW 89 dB DR continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to wide-band interferers

Session 5 Overview: WLAN Transceivers

A direct-conversion CMOS transceiver for 4.9-5.95 GHz multi-standard WLANs

A single chip CMOS transceiver for 802.11 a/b/g WLANs

A dual-band 802.11a/b/g radio in 0.18 /spl mu/m CMOS

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN

A 3.2 to 4 GHz, 0.25 /spl mu/m CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN

A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump

A 2.5dB NF direct-conversion receiver front-end for HiperLAN2/IEEE802.11a

4.3 GHz 44 /spl mu/W CMOS frequency divider

Session 6 Overview: Imaging

A 3.9 /spl mu/m pixel pitch VGA format 10 b digital image sensor with 1.5-transistor/pixel

A 1/4in 2M pixel CMOS image sensor with 1.75 transistor/pixel

CMOS image sensor using a floating diffusion driving buried photodiode

A CMOS image sensor with reset level control using dynamic reset current source for noise suppression

Combined linear-logarithmic CMOS image sensor

A 375 x 365 3D 1k frame/s range-finding image sensor with 394.5 kHz access rate and 0.2 subpixel accuracy

A CMOS single photon avalanche diode array for 3D imaging

A zero-sink-current Schmitt trigger and window-flexible counting circuit for fingerprint sensor/identifier

E1 To UWB or Not To Be

E2 Is the Golden Age of Analog Circuit Design Over?

SE4 Circuits and Applications for Organic Electronics

Session 7 Overview: TD: Scaling Trends

How scaling will change processor architecture

Designing outside rail constraints

Circuit design and noise considerations for future Blu-ray disc optical storage technology

3D interconnection and packaging: impending reality or still a dream?

A 160Gb/s interface design configuration for multichip LSI

A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

Electronic alignment for proximity communication

A high-voltage output driver in a standard 2.5 V 0.25 /spl mu/m CMOS technology

Session 8 Overview: Circuits for Digital Systems

100MPackets/s fully self-timed priority queue: FQ

A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform

Low-voltage-swing logic circuits for a 7GHz x86 integer core

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

Mixed body-bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

An on-chip active decoupling circuit to suppress crosstalk in deep sub-micron CMOS mixed-signal SoCs

A 4GHz 300mW 64b integer execution ALU with dual supply voltages in 90nm CMOS

Session 9 Overview: GBit-Transceivers

A low-jitter 16:1 MUX and a high-sensitivity 1:16 DEMUX with integrated 39.8 to 43GHz VCO for OC-768 communication systems

An 800 mW 10 Gb Ethernet transceiver in 0.13 /spl mu/m CMOS

A fully integrated 0.13 /spl mu/m CMOS 10 Gb Ethernet transceiver with XAUI interface

A 10 Gb/s SONET-compliant CMOS transceiver with low cross-talk and intrinsic jitter

A 12.5Gb/s CMOS BER test using a jitter-tolerant parallel CDR

A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18 /spl mu/m CMOS

A 20GHz VCO with 5GHz tuning range in 0.25 /spl mu/m SiGe BiCMOS

Session 10 Overview: Cellular Systems and Building Blocks

Digital-IF WCDMA handset transmitter IC in 0.25 /spl mu/m SiGe BiCMOS

An analog GFSK modulator in 0.35 /spl mu/m CMOS [Bluetooth transmitter applications]

Quad-band GSM/GPRS/EDGE polar loop transmitter

A 1.5V 28mA fully-integrated fast-locking quad-band GSM-GPRS transmitter with digital auto-calibration in 130nm CMOS

A polar modulator transmitter for EDGE

A 10/spl mu/s fast switching PLL synthesizer for a GSM/EDGE base-station

VSWR-protected silicon bipolar power amplifier with smooth power control slope

A small GSM power amplifier module using Si-LDMOS driver MMIC

Session 11 Overview: DRAM

A 0.6V 205MHz 19.5ns tRC 16Mb embedded DRAM

A 312MHz 16Mb random-cycle embedded DRAM macro with 73/spl mu/W power-down mode for mobile applications

A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

An 800MHz embedded DRAM with a concurrent refresh mode

A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture

A 1.6Gb/s/pin double-data-rate SDRAM with wave-pipelined CAS latency control

A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application

A 2Gb/s point-to-point heterogeneous voltage capable DRAM interface for capacity-scalable memory subsystems

Session 12 Overview: Biomicrosystems

Retinal prosthesis

A fully electronic DNA sensor with 128 positions and in-pixel A/D conversion

A 0.18/spl mu/m CMOS 10/sup -6/ lux bioluminescence detection system-on-chip

Capacitive sensor array for localization of bioparticles in CMOS lab-on-a-chip

A modular 32-site wireless neural stimulation microsystem

A power-efficient voltage-based neural tissue stimulator with energy recovery

Session 13 Overview: High-Speed Digital and Multi-Gb/s I/O

110Gb/s multiplexing and demultiplexing ICs

Under 0.5W 50Gb/s full-rate 4:1MUX and 1:4 DEMUX in 0.13/spl mu/m InP HEMT technology

A 108Gb/s 4:1 multiplexer in 0.13/spl mu/m SiGe-bipolar technology

A 43Gb/s 2:1 selector IC in 90nm CMOS technology

A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOS

An 8Gb/s capacitive-coupled receiver with high common-mode rejection for un-coded data

A 2Gb/s 2-tap DFE receiver for mult-drop single-ended signaling systems with reduced noise

An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory

Session 14 Overview: High-Speed A/D Converters

A 1.8V 1.6GS/s 8b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency

An 8b 600MS/s 200mW CMOS folding A/D converter using an amplifier preset technique

A 1.2V 220MS/s 10b pipeline ADC implemented in 0.13/spl mu/m digital CMOS

A 150MS/s 8b 71mW time-interleaved ADC in 0.18/spl mu/m CMOS

A 21mW 8b 125MS/s ADC occupying 0.09mm/sup 2/ in 0.13/spl mu/m CMOS

A 3b 40GS/s ADC-DAC in 0.12/spl mu/m SiGe

A 6b 600MHz 10mW ADC array in digital 90nm CMOS

Session 15 Overview: Wireless Consumer ICs

A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process

A dual-mode 802.11b/Bluetooth receiver in 0.25/spl mu/m BiCMOS

All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13/spl mu/m CMOS

A multi-mode 0.3-128kb/s transceiver for the 433/868/915MHz ISM bands in 0.25/spl mu/m CMOS

A 12GHz silicon bipolar receiver for digital satellite applications

A digital terrestrial television (ISDB-T) tuner for mobile applications

A 4/spl mu/A-quiescent-current dual-mode buck converter IC for cellular phone applications

Compact realization of active channel-select filters in wireless receivers

Session 16 Overview: TD: Emerging Technologies and Circuits

All-polymer thin film transistor fabricated by high-resolution ink-jet printing

Cut-and-paste organic FET customized ICs for application to artificial skin

A nonvolatile programmable solid electrolyte nanometer switch

A 180mV FFT processor using subthreshold circuit techniques

Si nanodevices for random number generating circuits for cryptographic security

Superconducting quantum storage and processing

SE5 Noise Coupling in Mixed-Signal/RF SoCs

E3 Processors and Performance: When Do GHz Hurt?

A single-flux-quantum logic prototype microprocessor

A 13GHz CMOS distributed oscillator using MEMS coupled transmission lines for low phase noise

E4 What is the Next Embedded Non-Volatile Memory Technology?

Session 17 Overview: MEMS and Sensors

Reconfigurable RF circuits based on integrated MEMS switches

A single-chip CMOS micro-hotplate array for hazardous-gas detection and material characterization

A 2.5V 14-bit /spl Sigma//spl Delta/ CMOS-SOI capacitive accelerometer

An ultra-low energy microcontroller for Smart Dust wireless sensor networks

A very low power CMOS mixed-signal IC for implantable pacemaker applications

A fourth-order /spl Sigma//spl Delta/ interface for micromachined inertial sensors

60-MHz wine-glass micromechanical-disk reference oscillator

Session 18 Overview: Consumer Signal Processing

A 1440/spl times/1080 pixels 30frames/s motion-JPEG2000 codec for HD movie transmission

81MS/s JPEG2000 single-chip encoder with rate-distortion optimization

An SoC with two multimedia DSPs and a RISC core for video compression applications

A 109.5mW 1.2V 600M texels/s 3-D graphics engine

An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU

A resume-standby application processor for 3G cellular phones

A DSL customer-premise equipment modem SoC with extended reach/rate for broadband bridging and routing

Session 19 Overview: Clock Generation and Distribution

A 4.6GHz resonant global clock distribution network

Parallel clocking: a multi-phase clock-network for 10GHz SoC

Notice of Violation of IEEE Publication Principles A 160-2550MHz CMOS active clock deskewing PLL using analog phase interpolation

Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers

On-chip jitter-spectrum-analyzer for high-speed digital designs

Design and analysis of a jitter-tolerant digital delay-locked-loop based fraction-of-clock delay line

Timing uncertainty measurements on the Power5 microprocessor

PowerTune: advanced frequency and power scaling on 64b PowerPC microprocessor

Session 20 Overview: Digital-to-Analog Converters

A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications

A 10b 250MS/s binary-weighted current-steering DAC

A 200MS/s 14b 97mW DAC in 0.18/spl mu/m CMOS

A 2GS/s 3b /spl Delta//spl Sigma/-modulated DAC with a tunable switched-capacitor bandpass DAC mismatch shaper

A 128f/sub s/ multi-bit /spl Sigma//spl Delta/ CMOS audio DAC with real-time DEM and 115dB SFDR

A 13b 1.1 MHz oversampled DAC with semidigital reconstruction filtering

A 110dB ternary PWM current-mode audio DAC with monolithic 2Vrms driver

Protection of audio amplifiers based on temperature measurements in power transistors

Session 21 Overview: RF Potpourri

Circular-geometry oscillators

A circular standing wave oscillator

An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers

A 3 to 10 GHz LNA using a wideband LC-ladder matching network

A fully integrated 13 GHz /spl Delta//spl Sigma/ fractional-n PLL in 0.13 /spl mu/m CMOS

A 17.1 to 17.3 GHz image-reject down-converter with phase-tunable LO using 3/spl times/ subharmonic injection locking

A fully integrated 24 GHz 8-path phased-array receiver in silicon

A low-loss phase shifter in 180 nm CMOS for multiple-antenna receivers

A 35.2-37.6 GHz LC VCO in a 70/100 GHz f/sub T//f/sub max/ SiGe technology

A monolithic low phase noise 1.7GHz CMOS VCO for zero-IF cellular CDMA receivers

A +110dBm IIP3 SiGe mixer with IM3 cancellation technique

Session 22 Overview: DSL and Multi-Gb/s I/O

A four-channel ADSL2+ analog front end for CO applications with 75mW per channel built in 0.13/spl mu/m CMOS

A 0.13/spl mu/m CMOS four-channel ADSL2+ analog front-end for CO applications with 75mW per channel

A 3 V CMOS quad-spectrum ADSL CPE analog front-end with 5 V integrated line driver

7th-order low-voltage CMOS POTS/ADSL splitter for DSL access multiplexer size reduction

A scalable 160Gb/s switch fabric processor with 320Gb/s memory bandwidth

A 4 Gb/s/pin dual-reference simultaneous bidirectional I/O circuit for memory-bus interface

A 3.6 Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM

Session 23 Overview: Channel Coding

A 600 MHz DSP with 24 Mb embedded DRAM with an enhanced instruction set for wireless communication

A 28.8 Mb/s 4/spl times/4 MIMO 3G high-speed downlink packet access receiver with normalized least mean square equalization

A highly-integrated 3G CDMA2000 1X cellular baseband chip with GSM/AMPS/GPS/Bluetooth/multimedia capabilities and ZIF RIF support

A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder

A 0.18 /spl mu/m CMOS front-end processor for a blu-ray disc recorder with an adaptive PRML

A CMOS SoC for 56/32/56/16 COMBO driver applications

A 1GHz CMOS analog-front-end for a partial-response read channel

Session 24 Overview: TD: Wireless Trends: Low-Power and 60GHz

A wireless integrated microsystem for environmental monitoring

A 0.9V 2.2mA multi-channel programmable FM receiver for hearing-aid applications in 0.25 /spl mu/m CMOS

AC-only RF ID tags for barcode replacement

Design of CMOS for 60GHz applications

60GHz transceiver circuits in SiGe bipolar technology

64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method

A 63 GHz VCO using a standard 0.25 /spl mu/m CMOS process

Millimeter-wave photonic integrated circuit technologies for high-speed wireless communications applications

Session 25 Overview: High-Resolution Nyquist ADCs

A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC

A 15 b 20 MS/s CMOS pipelined ADC with digital background calibration

A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter

A 1.8 V 14 b 10 MS/s pipelined ADC in 0.18 /spl mu/m CMOS with 99 dB SFDR

A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration

An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection

A 14 b-linear capacitor self-trimming pipelined ADC

An opamp with common-mode linearized input stage

Session 26 Overview: Optical and Fast I/O

Single-stage 378MHz 178k/spl Omega/ transimpedance amplifier with capacitive-coupled voltage dividers [optical fiber receiver applications]

3Gb/s monolithically integrated photodiode and pre-amplifier in standard 0.18/spl mu/m CMOS

Burst-mode receiver for 1.25Gb/s Ethernet PON with AGC and internally created reset signal

40Gb/s CMOS distributed amplifier for fiber-optic communication systems

A 12dBm 320GHz GBW distributed amplifier in a 0.12/spl mu/m SOI CMOS

40Gb/s amplifier and ESD protection circuit in 0.18/spl mu/m CMOS technology

A BiCMOS 10Gb/s adaptive cable equalizer

A 2 GHz CMOS variable-gain amplifier with 50 dB linear-in-magnitude controlled gain range for 10GBase-LX4 Ethernet

Output buffer impedance control and noise reduction using a speed-locked loop

A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process

Session 27 Overview: SRAM

Cosmic-ray immune latch circuit for 90nm technology and beyond

A 300MHz 25/spl mu/A/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

A 0.13/spl mu/m triple-Vt 9MB third level on-die cache for the Itanium/spl reg/ 2 processor

A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

Architecture and circuit techniques for a reconfigurable memory block

Per-bit sense amplifier scheme for 1GHz SRAM macro in sub-100nm CMOS technology

A digital circuit for a minimum distance search using an asynchronous bubble shift memory

A differential current-mode sensing method for high-noise-immunity, single-ended register files

A 90nm dual-port SRAM with 2.04 /spl mu/m/sup 2/ 8T-thin cell using dynamically-controlled column bias scheme

ISSCC 2004 Solid State Circuits Conference Tutorials

ISSCC 2004 Solid State Circuits Conference

ISSCC 2004 Solid State Circuits Conference gigahertz radio front ends: RF power amplifiers

ISSCC 2004 Solid State Circuits Conference Executive Committee

ISSCC 2004 Solid State Circuits Conference Program Committee

San Francisco Marriott Hotel location map

ISSCC 2005 call for papers

Timetable of ISSCC 2004 sessions

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

Proceedings ISSCC '95 - International Solid-State Circuits Conference

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1990 37th IEEE International Conference on Solid-State Circuits

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1975 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1974 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1972 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1971 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1970 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1969 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1968 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1967 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1966 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1965 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1964 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1962 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1961 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1957 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1956 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1955 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

A 3.9 /spl mu/m pixel pitch VGA format 10 b digital image sensor with 1.5-transistor/pixel

Content Provider	IEEE Xplore Digital Library
Author	Takahashi, H. Kinoshita, M. Morita, K. Shirai, T. Sato, T. Kimura, T. Yuzurihara, H. Inoue, S.
Copyright Year	2004
Description	Author affiliation: Canon, Ayase, Japan (Takahashi, H.; Kinoshita, M.; Morita, K.; Shirai, T.; Sato, T.; Kimura, T.; Yuzurihara, H.; Inoue, S.)
Abstract	A CMOS image sensor with a shared 1.5 transistor/pixel architecture and buried photodiode with complete charge transfer capability is described. The sensor achieves a 330 /spl mu/V noise floor and 50 pA/cm/sup 2/ dark current at 45/spl deg/C. The chip is fabricated in a thin planarized 0.35 /spl mu/m 1P2M CMOS process.
Starting Page	108
Ending Page	516
File Size	594046
Page Count	409
File Format	PDF
ISBN	0780382676
ISSN	01936530
DOI	10.1109/ISSCC.2004.1332617
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-02-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pixel Digital images Image sensors Photodiodes CMOS image sensors Clocks Charge transfer Turning Sensor phenomena and characterization CMOS process
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in