NDLI: Emerging technology and business solutions for system chips

Content Provider	IEEE Xplore Digital Library
Author	Lu, N.C.
Copyright Year	2004
Description	Author affiliation: Etron Technol., Hsinchu, Taiwan (Lu, N.C.)
Abstract	In three decades, the IC industry grew from nothing to current GSI levels (with 10/sup 9/ devices on a chip). Its major driving force has been the use of device scaling, which has been especially effective in enhancing the performance of digital chips. However, increasingly, diverse system applications have created an additional driving force - the development of more and more system chips with an increased need to integrate more diverse functionality (digital, analog, memory, RF, etc.) within a limited form factor. In addition to current SoCs on a 2D die, a trend for the coming decade is multidimensional die integration on interconnected substrates in a compact package. Correspondingly, a metric analyzing technology trends is presented. At the same time, beyond the innovative foundry/fabless business structure of the 1990s, new business models are evolving for the realization of system chips. Such models, leading to an effective solution called virtual vertical integration, is discussed. System-chip development must also be vertically integrated to achieve optimized performance, but advanced technologies required to realize such integration cover various horizontal segments of knowledge, such as multidimensional-die architecture design, circuit design, and related design automation, as well as novel testing and packaging techniques, leading-edge device and wafer-fabrication technologies, and solution-oriented software coding. In this regard, critical challenges are highlighted in terms of power partitioning, integrated design, and built-in quality assurance for known-good-die, signal integrity in field applications, and technology optimization across different segments. The parallelism of technology solutions with business models, and their conjoined optimization in the coming system-chip era, is illustrated in this paper.
Starting Page	25
Ending Page	31
File Size	646465
Page Count	7
File Format	PDF
ISBN	0780382676
ISSN	01936530
DOI	10.1109/ISSCC.2004.1332580
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-02-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit technology Multidimensional systems Packaging Design optimization Circuit testing Radio frequency Integrated circuit interconnections Foundries Computer architecture Circuit synthesis
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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