NDLI: An integrated 802.11a baseband and MAC processor

Content Provider	IEEE Xplore Digital Library
Author	Thomson, J. Baas, B. Cooper, E.M. Gilbert, J.M. Hsieh, G. Husted, P. Lokanathan, A. Kuskin, J.S. McCracken, D. McFarland, B. Meng, T.H. Nakahira, D. Ng, S. Rattehalli, M. Smith, J.L. Subramanian, R. Thon, L. Yi-Hsiu Wang Yu, R. Xiaoru Zhang
Copyright Year	2002
Description	Author affiliation: Atheros Commun., Sunnyvale, CA, USA (Thomson, J.)
Abstract	An 0.25 /spl mu/m CMOS mixed-signal baseband and MAC processor for the IEEE 802.11a WLAN standard in 0.25 /spl mu/m CMOS occupies 6.8/spl times/6.8 mm/sup 2/ and contains 4.0M transistors in a 196-pin BGA package. Power consumption for transmit and receive is 326 mW and 452 mW. Additional data rates up to 108 Mb/s are supported. The MAC is implemented using dedicated control and datapath logic, and includes registers that allow host software to configure and control its operation. This yields an overall design that is compact, power-efficient, and requires no off-chip RAM or program storage, yet is very flexible.
Sponsorship	IEEE Solid-State Circuits Soc.
Starting Page	126
Ending Page	451
File Size	289228
Page Count	326
File Format	PDF
ISBN	0780373359
DOI	10.1109/ISSCC.2002.992968
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-02-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Baseband Engines Protocols Wireless LAN Transmitters Logic Sleep Filtering Digital filters Code standards
Content Type	Text
Resource Type	Article

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