NDLI: A 4 GHz 40 dB PSRR PLL for an SOC application

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2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)

i-mode: the mobile Internet service of the 21st century

Broadband access: the last mile

Microprocessors for the new millennium: Challenges, opportunities, and new frontiers

A 3.3 V 1 Gb multi-level NAND flash memory with non-uniform threshold voltage distribution

A 126.6 mm/sup 2/ AND-type 512 Mb flash memory with 1.8 V power supply

A 1.8 V 64 Mb 100 MHz flexible read while write flash memory [in CMOS]

An embedded 1.2 V-read flash memory module in a 0.18 /spl mu/m logic process

A highly reliable 1T1C 1 Mb FRAM with novel ferro-programmable redundancy scheme

A nonvolatile ferroelectric RAM with common plate folded bit-line cell and enhanced data sensing scheme

A 76 mm/sup 2/ 8 Mb chain ferroelectric memory

A 13.5mW, 185 MSample/s /spl Delta//spl Sigma/-modulator for UMTS/GSM dual-standard IF reception

A 5 mW /spl Sigma//spl Delta/ modulator with 84 dB dynamic range for GSM/EDGE

A quadrature data-dependent DEM algorithm to improve image rejection of a complex /spl Sigma//spl Delta/ modulator

A 2.5 V broadband multi-bit /spl Sigma//spl Delta/ modulator with 95 dB dynamic range

A 1 V 10.7 MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using doublesampling finite-gain-compensation technique

A low-power reconfigurable analog-to-digital converter

A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25 /spl mu/m CMOS

A 2 Gb/s 21 CH low-latency transceiver circuit for inter-processor communication

3.2 GHz 6.4 Gb/s per wire signaling in 0.18 /spl mu/m CMOS

5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking

A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers

Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin /spl times/16 DDR SDRAM

Circuit design for a 2.2 GB/s memory interface

An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5 Gb/s optical communication

Fully-integrated SONET OC48 transceiver in standard CMOS

A 10 Gb/s CMOS clock and data recovery circuit with frequency detection

A 10 Gb/s 16:1 multiplexer and 10 GHz clock synthesizer in 0.25 /spl mu/m SiGe BiCMOS

A single-chip 10 Gb/s transceiver LSI using SiGe SOI/BiCMOS

A fully-integrated 40 Gb/s clock and data recovery/1:4 DEMUX IC in SiGe technology

A 10 kframe/s 0.18 /spl mu/m CMOS digital pixel sensor with pixel-level memory

A miniature imaging module for mobile applications

Arbitrated address event representation digital image sensor

A 48 kframe/s CMOS image sensor for real-time 3-D sensing and motion detection

A 128/spl times/128 CMOS imager with 4/spl times/128 bit-serial column-parallel PE array

A signal-processing CMOS image sensor using a simple analog operation

Autoscaling CMOS APS with customized increase of dynamic range

Genetic applets: biological integrated circuits for cellular control

The design and measurement of molecular electronic switches and memories

Strained Si surface channel MOSFETs for high-performance CMOS technology

FinFET-a quasi-planar double-gate MOSFET

Ultra-miniature high-Q filters and duplexers using FBAR technology

A 256 kb 3.0 V 1T1MTJ nonvolatile magnetoresistive RAM

A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS

A 6 b 1.1 GSample/s CMOS A/D converter

A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply

A 2.5 V 12 b 54 MSample/s 0.25 /spl mu/m CMOS ADC in 1 mm/sup 2/

A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist

A 14 b 40 MSample/s pipelined ADC with DFCA

A 90 mW MPEG4 video codec LSI with the capability for core profile

A 80/20 MHz 160 mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications

One-chip 15 frame/s mega-pixel real-time image processor

A 250 MHz single-chip multiprocessor for A/V signal processing

A 4 GOPS 3 way-VLIW image recognition processor based on a configurable media-processor

A 150 MHz graphics rendering processor with 256 Mb embedded DRAM

A 1.5 W class-F RF power amplifier in 0.2 /spl mu/m CMOS technology

A CMOS RF power amplifier with parallel amplification for efficient power control

A 1 W 0.35 /spl mu/m CMOS power amplifier for GSM-1800 with 45% PAE

A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers

A +18 dBm IIP3 LNA in 0.35 /spl mu/m CMOS

A wideband 1.3 GHz PLL for transmit remodulation suppression

Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell

An architecture for compact associative memories with deca-ns nearest-match capability up to large distances

SRAM current-sense amplifier with fully-compensated bit line multiplexer

Abnormal leakage suppression (ALS) scheme for low standby current SRAMs

A 900 MHz 2.25 MB cache with on-chip CPU now in Cu SOI

Power-efficient application-specific VLIW processor for turbo decoding

A mixed-signal 0.18 /spl mu/m CMOS SOC for DVD systems with 432 MS/s PRML read channel and 16 Mb embedded DRAM

A 700 Mb/s BiCMOS read channel integrated circuit

A 300 MHz mixed-signal FDTS/DFE disk read channel in 0.6 /spl mu/m CMOS

A 1 Gb/s read/write-preamplifier for hard-disk-drive applications

A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels

A 16 b accurate CMOS laser driver IC with 500 mA output current and 1.5 ns rise time

A fully-integrated single-chip SOC for Bluetooth

A fully-integrated CMOS RFIC for Bluetooth applications

A 2.4 GHz CMOS transceiver for Bluetooth

A 22 mW Bluetooth RF transceiver with direct RF modulation and on-chip IF filtering

A zero-IF single-chip transceiver for up to 22 Mb/s QPSK 802.11b wireless LAN

A single-chip 2.4 GHz RF transceiver LSI with a wide-range FV conversion demodulator

A fully-integrated 5 GHz CMOS wireless-LAN receiver

A 0.6-2.5 GBaud CMOS tracked 3/spl times/ oversampling transceiver with dead-zone phase detection for robust clock/data recovery

A 2.75 Gb/s CMOS clock recovery circuit with broad capture range

A Si bipolar laser diode driver/receiver chip set for 4-channel 5 Gb/s parallel optical interconnection

A 1 V 1 mW CMOS front-end with on-chip dynamic gate biasing for a 75 Mb/s optical receiver

A redundant multi-valued logic for 10 Gb/s CMOS demultiplexer IC

A chipset for scalable QoS-preserving protocol-independent packet switch fabrics

A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

40 Gb/s ASIC switch design using low-jitter clock recovery

A scalable performance 32 b microprocessor

Physical design of a fourth-generation POWER GHz microprocessor

A process-portable 64b embedded microprocessor with graphics extensions and a 3.6 GB/s interface

First-generation MAJC dual microprocessor

A 1.1 GHz first 64 b generation 2900 microprocessor

A 1.2 GHz Alpha microprocessor with 44.8 GB/s chip pin bandwidth

A CMOS multi-parameter biochemical microsensor with temperature control and signal interfacing

A single-chip CMOS resonant beam gas sensor

Integrated Hall sensor array microsystem

A capacitive fingerprint sensor with low-temperature poly-Si TFTs

A CMOS photosensor array for 3D imaging using pulsed laser

A versatile micro-power high-voltage flat-panel display driver

100 frames/s CMOS range image sensor

Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip

Neuromorphic vision chip fabricated using three-dimensional integration technology

3-D assembly interposer technology for next-generation integrated systems

Millimeter-wave characteristics of SiGe heterojunction bipolar transistors and monolithic interconnects in silicon technologies

Backside infrared probing for static voltage drop and dynamic timing measurements

Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution

Sea of leads: a disruptive paradigm for a system-on-a-chip (SoC)

A 22 mA 3.7 dB NF direct conversion receiver for 3G WCDMA

A fully integrated CMOS RF front-end with on-chip VCO for WCDMA applications

A 1 V 12 mW 2 GHz receiver with 49 dB image rejection in CMOS/SIMOX

A 930 MHz CMOS DC-offset-free direct-conversion 4-FSK receiver

A 900 MHz dual conversion low-IF GSM receiver in 0.35 /spl mu/m CMOS

A 2 GHz CMOS image-reject receiver with sign-sign LMS calibration

A 285 mW CMOS single chip analog front end for G.SHDSL

A CMOS direct access arrangement using digital capacitive isolation

A high-voltage line driver (HVLDR) for combined voice and data services

An ADSL central office analog front-end integrating actively-terminated line driver, receiver and filters

SOPA: A high-efficiency line driver in 0.35 /spl mu/m CMOS using a self-oscillating power amplifier

A DSP based receiver for 1000BASE-T PHY

A CMOS transceiver analog front-end for gigabit ethernet over CAT-5 cables

A 1.8 GHz Instruction Window Buffer

A low power SOI adder using reduced-swing charge recycling circuits

Sub-500 ps 64 b ALUs in 0.18 /spl mu/m SOI/bulk CMOS: Design & scaling trends

Design and migration challenges for an Alpha microprocessor in a 0.18 /spl mu/m copper process

A 1 GHz PA-RISC processor

A 0.18 /spl mu/m CMOS IA32 microprocessor with a 4 GHz integer execution unit

A universal cable set-top box system on a chip

An energy-efficient IEEE 1363-based reconfigurable public-key cryptography processor

A self-contained 100 /spl mu/W multirate FSK receiver ASIC

A single-chip band-segmented-transmission OFDM demodulator for digital terrestrial television broadcasting

A digital 72 Mb/s 64-QAM OFDM transceiver for 5 GHz wireless LAN in 0.18 /spl mu/m CMOS

A single chip PHY COFDM modem for IEEE 802.11a with integrated ADCs and DACs

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

ChipOS: Open power-management platform to overcome the power crisis in future LSIs

Elastic interconnects: repeater-inserted long wiring capable of compressing and decompressing data

The implementation of two multiprocessor DSPs: a design methodology case study

A GSM 2+ conversion signal processor for continuous full-duplex EDGE/GPRS applications

A fully-configurable GSM BTS controller and GMSK-EDGE base-band transmitter IC

A multicarrier GMSK modulator for base station

A synchronous dual-output switching dc-dc converter using multibit noise-shaped switch control

Dynamically biased 1 MHz low-pass filter with 61 dB peak SNR and 112 dB input range

A 200 nV offset 6.5 nV//spl radic/Hz noise PSD 5.6 kHz chopper instrumentation amplifier in 1 /spl mu/m digital CMOS

A filtering technique to lower oscillator phase noise

A 12 b 500 MSample/s current-steering CMOS D/A converter

A 1.9 GHz Si active LC filter with on-chip automatic tuning

A 0.25 /spl mu/m CMOS 17 GHz VCO

A 50 GHz VCO in 0.25 /spl mu/m CMOS

Wideband BiCMOS VCO for GSM/UMTS direct conversion receivers

A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture

A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse

A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture

A 1.0 V 230 MHz column-access embedded DRAM macro for portable MPEG applications

A 1.43 GHz per data I/O 16 Mb DDR low-power embedded DRAM macro for a 3D graphics engine

An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester

A 4 GHz 40 dB PSRR PLL for an SOC application

A low jitter 125-1250 MHz process independent 0.18 /spl mu/m CMOS PLL based on a sample-reset loop filter

A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications

2.5 GHz 4-phase clock generator with scalable and no feedback loop architecture

Multi-gigahertz low-power low-skew rotary clock scheme

The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor

Multi-GHz clocking scheme for Intel(R) Pentium(R) 4 microprocessor

A triple-band 900/1800/1900 MHz low-power image-reject front-end for GSM

A 0.8 dB NF ESD-protected 9 mW CMOS LNA

A 19 GHz 0.5 mW 0.35 /spl mu/m CMOS frequency divider with shunt-peaking locking-range enhancement

A 2 GHz down-converter with a 3 dB bandwidth of 600 MHz using LO signal suppressing output buffer

3 V GSM base station RF receivers using 0.25 /spl mu/m BiCMOS

A 2.4 GHz 34 mW CMOS transceiver for frequency-hopping and direct-sequence applications

SiGe BiCMOS broadband phase-aligner circuit from 1 Gb/s to 11 Gb/s

Index of authors

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

Proceedings ISSCC '95 - International Solid-State Circuits Conference

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1990 37th IEEE International Conference on Solid-State Circuits

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1975 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1974 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1972 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1971 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1970 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1969 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1968 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1967 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1966 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1965 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1964 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1962 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1961 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1957 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1956 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1955 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

A 4 GHz 40 dB PSRR PLL for an SOC application

Content Provider	IEEE Xplore Digital Library
Author	Ingino, J.M.
Copyright Year	2001
Description	Author affiliation: SiByte Inc., Santa Clara, CA, USA (Ingino, J.M.)
Abstract	This PLL achieves >40dB power-supply-rejection ratio (PSRR) operating at 4GHz. The PLL is for use in a high-speed SOC that operates at internal clock frequencies exceeding 2GHz. The high level of noise rejection is achieved with a high-bandwidth voltage regulator that provides a nominally noise-free 2.OV supply to the PLL sensitive analog blocks. Previous PLL designs employ voltage regulators to filter out supply noise but generally are limited to PSRRs <25dB. The regulator is powered using the SOC 3.3V I/O power supply.
Sponsorship	IEEE Solid-State Circuits Soc.
Starting Page	392
Ending Page	393
File Size	464412
Page Count	2
File Format	PDF
ISBN	0780366085
ISSN	01936530
DOI	10.1109/ISSCC.2001.912688
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-02-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops System-on-a-chip Voltage Clocks Regulators Noise level Frequency Voltage-controlled oscillators Circuit noise Charge pumps
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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