NDLI: A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture

Content Provider	IEEE Xplore Digital Library
Author	Kirihata, T. Mueller, G. Clinton, M. Loeffler, S. Ji, B. Terletzki, H. Hanson, D. Chorng-Lil Hwang Lehmann, G. Storaska, D. Daniel, G. Hsu, L. Weinfurtner, O. Boehler, T. Schnell, J. Frankowsky, G. Netis, D. Ross, J. Reith, A. Kiehl, O. Wordeman, M.
Copyright Year	2001
Description	Author affiliation: Semicond. R&D Center, IBM Microelectron., Hopewell Junction, NY, USA (Kirihata, T.)
Abstract	This 512 Mb DDR2 SDRAM is designed with the DDR2 features being standardized by JEDEC. The SDRAM uses a four-quadrant architecture, each 128 Mb quadrant containing 16 k rows x 8 k columns. A 6.6F/sup 2/ (2.2F×3F) deep trench cell with a vertical access gate is employed. The wordline pitch is increased by 10% and the bitline pitch by 50%, yet the cell area is reduced to as little as 82.5% that of the 8F/sup 2/ cell. Each 128 Mb quadrant is partitioned into sixteen 8 Mb blocks horizontally. It is also partitioned into sixteen 8 Mb segments vertically. These partitions configure a 512 kb array, each containing 1024 wordlines (WLs) and 512 bitlines (BLs). A total of 16×16 512 kb arrays are arranged in a matrix in each 128 Mb quadrant. A hierarchical row decoder block (HRDEC) drives a master wordline (MWL) on a 2nd level metal (M2). A local wordline decoder block (LRDEC) then redrives the MWL to control a local W-silicide wordline (LWL).
Sponsorship	IEEE Solid-State Circuits Soc.
Starting Page	382
Ending Page	383
File Size	348874
Page Count	2
File Format	PDF
ISBN	0780366085
ISSN	01936530
DOI	10.1109/ISSCC.2001.912683
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-02-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SDRAM Content addressable storage Decoding Delay Clocks Microelectronics Research and development Noise cancellation Topology Logic
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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