NDLI: Complementary sidewall-spacer-diffused ultrashallow SD extension process for damascene independently-double-gated SOI CMOS

Content Provider	IEEE Xplore Digital Library
Author	Parke, S. Goldston, M. Hackler, D. DeGregorio, K. Hayhurst, R. Horvath, A. Parsa, S.
Copyright Year	2004
Description	Author affiliation: American Semicond. Inc., Boise, ID, USA (Parke, S.; Goldston, M.; Hackler, D.; DeGregorio, K.; Hayhurst, R.)
Abstract	We introduce a new SOI CMOS device, Flexfet/sup TM/, that utilizes a gate trench etched through thick implanted SD regions to self-align a hyper retrograde implanted bottom gate with a metal top gate, and create an ultra-thin channel region. Rapid thermal diffusion from complementary PSG/BSG sidewall spacers was used to achieve 15 nm USJ SDEs that connect to deeper implanted SD junctions. Effectively raised SDs are achieved without using selective epi. The sidewall spacers also narrow the trench opening below the minimum feature size, and are used to self-align the implanted bottom gate and the high-K/metal top gate.
Sponsorship	IEEE Electron Devices Soc
Starting Page	104
Ending Page	105
File Size	222034
Page Count	2
File Format	PDF
ISBN	0780384970
DOI	10.1109/SOI.2004.1391575
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS process Annealing Plasma applications Lamps Optical device fabrication Silicon germanium Germanium silicon alloys Plasma devices Etching Voltage
Content Type	Text
Resource Type	Article

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