NDLI: “Free” Razor: A novel adaptive voltage scaling low power technique for data path SoC designs

Content Provider	IEEE Xplore Digital Library
Author	Yuejian Wu Thomson, S. Han Sun Krause, D. Song Yu Kurio, G.
Copyright Year	2012
Description	Author affiliation: Infinera, 140 Caspian Ct. Sunn, vale, CA, USA (Song Yu; Kurio, G.) \|\| Infinera, 222-555 Legget Dr. Ottawa, ON. Canada (Yuejian Wu; Thomson, S.; Han Sun; Krause, D.)
Abstract	This paper proposes a novel adaptive voltage scaling low power design methodology for large System on Chip (SoC) that demands constant data throughput. The proposed technique scales the supply voltage to the SoC based on operating conditions and bit error rate (BER) margin available in a system. It allows occasional timing errors in the circuit and relies on a forward error correction (FEC) that exists in the system to correct the errors. As a result, the proposed technique requires no hardware overhead but yields significant power savings. More importantly, it does not require any circuit modification based on place and route, thus easy to implement and has no impact on time to market. The new technique has been implemented in a complex telecom SoC design and silicon measurement shows power savings up to 46%.
Starting Page	33
Ending Page	38
File Size	761636
Page Count	6
File Format	PDF
ISBN	9781467312943
ISSN	21641706
e-ISBN	9781467312950
DOI	10.1109/SOCC.2012.6398373
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bit error rate Forward error correction Sensors Timing System-on-a-chip Power dissipation Voltage measurement voltage scaling Low power design
Content Type	Text
Resource Type	Article

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